GP2015 datasheet(3/24 Pages) MITEL

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GP2015

POWER-DOWN CAPABILITY

A power down function is provided on the GP2015, to

limit power consumption. This powers down the majority of

the circuit except the “power-on reset” function (see below).

If the power down feature is not required, the Power-

down input, PDn (pin 19), should be connected to 0V dc

(=Vee/Ground).

POWER-ON RESET FUNCTION

The GP2015 includes a voltage detector which

operates from the digital interface supply. This circuit is used

to produce a TTL logic low output while the GPS receiver

power supply is switching on, and produces a logic high

output when the power supply voltage has achieved a nominal

value. This output can be used to disable the GP2021

correlator while the power supply is switching on. An internal

bandgap reference of approximately +1.21V is compared

with the voltage on a sense pin, PRef (pin 8); when the

voltage on this pin exceeds the reference, a TTL logic high

level appears at the Power-on Reset output, PReset (pin 9).

Thus, if the sense input voltage is derived from an external

resistive divider from the Digital Interface supply, VDD(IO) (pin

16), such that the sense voltage at nominal VCC is VS, then the

supply threshold, Vcc(thresh), at which the PReset output

goes to logic high is:-

For a VCC (nom) of 5.0V, VCC (thresh) may be set to approx.

4.0V, giving VS of 1.5V.

For a VCC (nom) of 3.0V, VCC (thresh) may be set to approx.

2.4V, giving VS of 1.5V.

ADDITIONAL INFORMATION

All the digital inputs and outputs can use a separate

power supply to help prevent digital switching transitions

interacting with the analog sections of the device, and as an

additional precaution, the digital inputs and outputs are on

the opposite side of the device to the critical analog pins.

The IF output is fed to a 2-bit quantiser which provides

sign and magnitude (MSB and LSB) outputs. The magnitude

data controls the AGC loop, such that on average the magnitude

bit is set (high) 30% of the time. The AGC time constant is set

by an external capacitor.

The sign and magnitude data, SIGN (pin 15) and MAG (pin

14), are latched by the rising edge of the sample clock, CLK

(pin 11), which is normally derived from the correlator; the

GP2021 provides a 5.714MHz (=40/7) clock, giving a sampled

IF centred on 1.405MHz.

The Digital Interface circuits use a separate power-supply,

VDD(IO), which would normally be shared with the correlator to

minimise crosstalk between the analog and digital sections of

the device.

ON-CHIP PHASE-LOCKED LOOP SYNTHESISER

All of the local oscillator signals are derived from an on

chip phase locked loop synthesiser. This includes a 1400MHz

VCO complete with on-chip tank circuit, dividers and phase

detector, with external loop filter components. A 10.000MHz

reference frequency is required for the PLL. This can be

achieved by attaching an external 10.000MHz crystal to the

on-chip PLL reference oscillator (see figure 5). However in

most applications the user will need an external source, such

as a TCXO, to provide greater frequency stability (see figure

6). An external reference should be ac coupled to REF2 (pin

27); REF 1 (pin 28) should be left open circuit.

The three local oscillator signals 1400MHz, 140.0MHz

and 31.11MHz are derived from the 1400MHz synthesiser

output. The synthesiser also provides a 40 MHz balanced

differential output clock (pins 16 & 17) which can be used to

clock the GP2021 correlator. The clock is a low level differential

signal which helps minimise interference with the analog

areas of the circuit. A PLL lock-detect output, LD (pin 21), is

also provided, which is logic high when the PLL is phase-

locked to the 10.000MHz reference signal.

The VCO power-supply incorporates an on-chip

regulator to improve the noise-immunity of the PLL. This

feature is only available when operating with a 5 volt (nominal)

supply which is regulated to 3.3 volts internally. This internal

regulated supply is referenced to VCC(OSC) (pin 5). Figure 7

shows the required connections for both 3 volt and 5 volt

operation.

A further feature of the circuit is the TEST input (pin 20).

When this input is held high the PLL is unlocked with the VCO

at its maximum frequency.

VS = VCC (nom) x 1.21

VCC (thresh)

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