GP2015 datasheet(6/24 Pages) MITEL

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GP2015

PIN DESCRIPTIONS

All VEE and VCC/VDD pins must be connected to ensure correct operation

Pin No.

Signal Name

Input/Output

Description

IFOutput

Output

IF Test output.

Connected to output of Stage 3 prior to the A to D converter.

A series 1k

Ω resistor is incorporated for buffering purposes.

PLL Filter 1

Output

PLL Filter 1.

Connected to the bias network within the on-chip VCO. An

external PLL loop filter network should be connected between

this pin and PLL Filt 2 (see below).

PLL Filter 2

Output

PLL Filter 2.

Connected to the varactor diodes within the on-chip VCO. An

external PLL loop filter network should be connected between

this pin and PLL Filt 1 (see above).

4,6

VEE (OSC)

Input

Negative supply to the on-chip VCO. (See Note 1)

5VCC (OSC)

Input

Positive supply to the on-chip VCO.

7VEE (REG)

Input

Negative supply to the VCO regulator.

This must be connected to GND.

PRef

Input

Power-on Reset Reference input.

An on-chip comparator produces a logic HI when the PRef

input voltage exceeds +1.21V. (Nom) (See Page 3)

PReset

Output

Power-on Reset Output.

A TTL compatible output controlled by the Power-on reset

comparator (See above). This output remains active even

when the chip is powered down. (See pin 19 - PDn).

VEE (IO)

Input

Negative supply to the Digital Interface. (See Note 2)

CLK

Input

Sample Clock input from the correlator chip.

A TTL compatible input (which operates at 5.714MHz if used

with GP2021 correlator device) used to clock the MAG & SIGN

output latches, on the rising edge of the CLK signal.

12, 13

N/C

Not connected. (See Note 4)

MAG

Output

Magnitude bit data output.

A TTL compatible signal, representing the

magnitude of the

mixed down IF signal. Derived from the on-chip 2-bit A to D

converter, synchronised to the CLK input clock signal.

SIGN

Output

Sign bit data output.

A TTL compatible signal, representing the

polarity of the mixed

down IF signal. Derived from the on-chip 2-bit A to D converter,

synchronised to the CLK input clock signal.

OPClk-

Output

40MHz Clock output - inverse phase.

One side of a balanced differential output clock, with opposite

polarity to Pin 17 - OPClk+. Used to drive a master-clock signal

within the correlator chip.

OPClk+

Output

40MHz Clock output - true phase.

Other side of a balanced differential output clock set, with

opposite polarity to Pin 16 - OPClk-. Used to drive a master-

clock signal within the correlator chip.

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