SM5844 datasheet(13/26 Pages) NPC

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SM5844AF

NIPPON PRECISION CIRCUITS—13

Microcontroller Interface (MCOM, MDT, MCK, MLEN)

When MCOM is HIGH, MDT (data), MCK (clock)

and MLEN (latch enable clock) interface pins are

used.

Input data on MDT is synchronized to the MCK

clock. Data is read into the input stage shift register

on the rising edge of MCK. Accordingly, the input

data should change on the falling edge of MCK.

Input data enters an internal SIPO (serial-to-parallel

converter register), and then the parallel data is

latched into the mode register on the rising edge of

the latch enable clock MLEN.

The mode register addressed is determined by the 1st

bit of the 12 data bits before MLEN goes HIGH. If

this bit is LOW, then the data is read into the

attenuation data register as shown in ﬁgure 1. If this

bit is HIGH, then the data is read into the mode ﬂag

in the mode ﬂag register is described in table 1.

Figure 1. Attenuation data format (B1 = LOW)

Figure 2. Mode ﬂag data format (B1 = HIGH)

MCK

MDT

MLEN

MCK and MLEN can also follow the dotted lines.

LOW

B10

MSB

B11

a10

B12

LSB

MCK

MDT

MLEN

MCK and MLEN can also follow the dotted lines.

HIGH

Not used

FTST1

FRATE

F12DB

FFSI1

B10

FFSI2

B11

FDEEM

B12

* *

FTST2

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