Digital main blocks

LIS3DE

20/46

DocID023719 Rev 3

An overrun interrupt can be enabled, INT1_OVERRUN = '1' in the CTRL_REG3 (22h)

register, in order to read the entire FIFO content at once. If, in the application, it is

mandatory not to lose data and it is not possible to read at least one sample for each axis

within one ODR period, a watermark interrupt can be enabled in order to read partially the

FIFO and leave memory slots free for incoming data.

Setting the FTH [4:0] bit in the FIFO_CTRL_REG (2Eh) register to value N, the number of X,

Y and Z data samples that should be read at the watermark interrupt rising is up to (N+1).

5.1.4

Stream-to-FIFO mode

In Stream-to-FIFO mode, data from the X, Y and Z accelerometer channels are collected in

a combination of Stream mode and FIFO mode; the FIFO buffer starts operating in Stream

mode and switches to FIFO mode when the selected interrupt occurs.

The FIFO operating mode changes according to the INT1 pin value if the TR bit is set to ‘0’

in the FIFO_CTRL_REG (2Eh) register or the INT2 pin value if the TR bit is set to ‘1’ in the

FIFO_CTRL_REG (2Eh) register.

When the interrupt pin is selected and the interrupt event is configured on the related pin,

the FIFO operates in Stream mode if the pin value is equal to ‘0’ and it operates in FIFO

mode if the pin value is equal to ‘1’. The switch mode is dynamically performed according to

the pin value.

Stream-to-FIFO can be used in order to analyze the sample history that generated an

interrupt; the standard operation is to read FIFO content when FIFO mode is triggered and

the FIFO buffer is full and stopped.

5.1.5

Retrieving data from FIFO

FIFO reads must start from register 28h.

FIFO X, Y and Z data are read from OUT_X (29h), OUT_Y (2Bh) and OUT_Z (2Dh). When

the FIFO is in Stream, Stream-to-FIFO or FIFO mode, a read operation to the OUT_X (29h),

OUT_Y (2Bh) and OUT_Z (2Dh) registers provides the data stored in the FIFO. Each time

data is read from the FIFO, the oldest X, Y and Z data are placed in the OUT_X (29h),

can be used.

d. The read address is automatically updated by the device and rolls back to 0x28 when register 0x2D is reached.

In order to read all FIFO levels in a multiple bytes read, 196 bytes (6 output registers by 32 levels) must be

read. FIFO reads must start from register 0x28 for output update and 0x2D for FIFO pointer update.