1

1

C

159 nF

2

1 k

N+]

5





b

b

b

3dB_A1+

8

1

1

f

1 kHz

2

R

C

5





b

b

b

2

5

R

R

10 k

2

§

·

:

¨

¸

©

¹

2

R

0.5 V

5 V

2 100 k

§

·

˜

¨

¸

˜

©

¹

REF3312, REF3318, REF3320, REF3325, REF3330, REF3333

www.ti.com

SBOS392E – AUGUST 2007 – REVISED OCTOBER 2014

The 3.3-V system supply voltage that powers the MSP430 can also supply other devices, and therefore may

have regulation and noise issues. The REF3330 creates an accurate and stable 3.0 V output used by the op

200 mV; therefore, as long as the input supply remains above 3.2 V, the REF3330 produces a regulated 3.0 V

output. The output current for the REF33xx series is specified at ±5 mA, as shown in Figure 9, and is sufficient

for the REF3312 and a low-power op amp.

10.2.1.2.4.2

Op Amp

The OPA317 op amp is used because of low offset voltage, low offset voltage drift, CMRR, and low power

consumption. The dc specifications for the OPA317 can be seen in the OPA317 data sheet, SBOS682, available

for download from www.ti.com. The maximum offset of 100 µV accounts for only 0.001% of the full-scale signal,

and the low-drift reduces temperature drift effects. Therefore, as previously mentioned, most of the error in this

design is from the reference accuracy and passive component tolerances.

10.2.1.2.5

Input Attenuation and Level Shifting

For this design, the bipolar ±5-V input must be attenuated and level shifted so the differential voltage is within the

±5 V input. Scaling the output this way also increases the allowable input range to ±6 V, and allows for some

underscale and overscale voltage measurement and protection.

Use Equation 12 to scale the ±5-V input to a ±0.5-V differential voltage, as shown in Equation 15.

where

•

(15)

can be selected to increase the input impedance at the expense of input noise.

where

•

(16)

without creating an impedance too weak to drive the ADC input.

10.2.1.2.6

Input Filtering

The MSP430 ADC is configured to run from the 1.1-MHz SMCLK with an oversampling rate (OSR) of 256,

yielding a sample rate of roughly 4.3 kHz. The input filter cutoff frequency is set to 1 kHz in order to limit the input

low-pass filter, thereby reducing stability concerns.

where

•

(17)

The A1– input of the delta-sigma (

ΔΣ) converter is not buffered, and therefore requires a large capacitor to

supply the charge for the internal sampling capacitor. A 47-

μF capacitor is selected, resulting in the cutoff

frequency shown in Equation 18.

Copyright © 2007–2014, Texas Instruments Incorporated

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Product Folder Links: REF3312 REF3318 REF3320 REF3325 REF3330 REF3333