ADP5300

Data Sheet

Rev. 0 | Page 14 of 21

THEORY OF OPERATION

The ADP5300 is a high efficient, ultralow quiescent current,

step-down regulator in a 10-lead LFCSP package to meet

demanding performance and board space requirements. The

device enables direct connection to a wide input voltage range of

2.15 V to 6.50 V, allowing the use of multiple alkaline/NiMH or,

Li-Ion cells and other power sources.

BUCK REGULATOR OPERATIONAL MODES

PWM Mode

In PWM mode, the buck regulator in the ADP5300 operates at

a fixed frequency that is set by an internal oscillator. At the start

of each oscillator cycle, the high-side MOSFET switch turns on

and sends a positive voltage across the inductor. The inductor

current increases until the current sense signal exceeds the peak

inductor current threshold, which turns off the high-side MOSFET

switch. This threshold is set by the error amplifier output. During

the high-side MOSFET off time, the inductor current decreases

through the low-side MOSFET until the next oscillator clock

pulse starts a new cycle.

Hysteresis Mode

In hysteresis mode, the buck regulator in the ADP5300 charges

the output voltage slightly higher than its nominal output voltage

with PWM pulses by regulating the constant peak inductor

current. When the output voltage increases until the output

sense signal exceeds the hysteresis upper threshold, the regulator

enters standby mode. In standby mode, the high-side and low-side

MOSFETs and a majority of the circuitry are disabled to allow a

low quiescent current as well as high efficiency performance.

During standby mode, the output capacitor supplies energy into

the load, and the output voltage decreases until it falls below the

hysteresis comparator lower threshold. The buck regulator wakes

up and generates the PWM pulses to charge the output again.

Because the output voltage occasionally enters standby mode

and then recovers, the output voltage ripple in hysteresis mode

is larger than the ripple in PWM mode.

Mode Selection

The ADP5300 includes the SYNC/MODE pin to allow flexible

configuration in hysteresis mode or PWM mode.

When a logic high level is applied to the SYNC/MODE pin, the

buck regulator is forced to operate in PWM mode. In PWM mode,

the regulator can supply up to 500 mA of output current. The

regulator can provide lower output ripple and output noise in

PWM mode, which is useful for noise sensitive applications.

When a logic low level is applied to the SYNC/MODE pin, the

buck regulator is forced to operate in hysteresis mode. In hysteresis

mode, the regulator draws only 180 nA of quiescent current

typical to regulate the output under zero load, which allows the

regulator to act as a keep-alive power supply in a battery-powered

system. In hysteresis mode, the regulator supplies up to 50 mA of

output current with a relatively large output ripple compared to

PWM mode.

The user can alternate between hysteresis mode and PWM mode

during operation. The flexible configuration capability during

operation of the device enables efficient power management to

meet high efficiency and low output ripple requirements when

the system switches between active mode and standby mode.

OSILLATOR AND SYNCHRONIZATION

The ADP5300 operates at a 2 MHz switching frequency typical

in PWM operation mode.

The switching frequency of the ADP5300 can be synchronized

to an external clock with a frequency range from 1.2 MHz to

2.5 MHz. The ADP5300 automatically detects the presence of an

external clock applied to the SYNC/MODE pin, and the switching

frequency transitions to the frequency of the external clock.

When the external clock signal stops, the device automatically

switches back to the internal clock.

ADJUSTABLE AND FIXED OUTPUT VOLTAGES

The ADP5300 provides adjustable output voltage settings by

connecting one resistor through the VID pin to AGND. The

VID detection circuitry works in the start-up period, and the

voltage ID code is sampled and held in the internal register and

does not change until the next power recycle. Furthermore, the

ADP5300 provides a fixed output voltage programmed via the

factory fuse. In this condition, connect the VID pin to the

PVIN pin.

For the output voltage settings, the feedback resistor divider is

built into the ADP5300, and the feedback pin (FB) must be tied

directly to the output. An ultralow power voltage reference and

an integrated high impedance (50 MΩ typical) feedback divider

network contribute to the low quiescent current. Table 5 lists the

output voltage options by the VID pin configurations. A 1%

accuracy resistor through VID to ground is recommended.

VID Configuration

Factory Option 0

Factory Option 1

Short to Ground

3.0

3.1

Short to PVIN

2.5

1.3

3.6

5.0

3.3

4.5

2.9

4.2

2.8

3.9

2.7

3.4

2.6

3.2

2.4

1.9

2.3

1.7

2.2

1.6

2.1

1.4

2.0

1.1

1.8

1.0

1.5

0.9

1.2

0.8