USB2533 datasheet(37/50 Pages) MICROCHIP

37 / 50 page

USB 2.0 Hi-Speed 3-Port Hub Controller

Datasheet

 2014 Microchip Technology Inc.

DS00001702A-page 37

4. The external crystal oscillator is halted.

5. The PLL is halted.

Note: All power supplies must have reached the operating levels mandated in Section 9.2, "Operating

Conditions**," on page 41, prior to (or coincident with) the assertion of RESET_N.

8.3.3

USB Bus Reset

In response to the upstream port signaling a reset to the device, the device performs the following:

Note: The device does not propagate the upstream USB reset to downstream devices.

1. Sets default address to 0.

2. Sets configuration to: Unconfigured.

3. Moves device from suspended to active (if suspended).

4. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the

reset sequence.

The host then configures the device in accordance with the USB Specification.

8.4

Link Power Management (LPM)

The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states per

the USB 2.0 Link Power Management Addendum. These supported LPM states offer low transitional

latencies in the tens of microseconds versus the much longer latencies of the traditional USB

suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8.3. For

additional information, refer to the USB 2.0 Link Power Management Addendum.

Note: State change timing is approximate and is measured by change in power consumption.

Note: System clocks are stopped only in suspend mode or when power is removed from the device.

8.5

Remote Wakeup Indicator (SUSP_IND)

The remote wakeup indicator feature uses the SUSP_IND as a side band signal to wake up the host

when in suspend. This feature is enabled and disabled via the HUB_RESUME_INHIBIT configuration

bit in the hub configuration space register CFG3. The only way to control the bit is by configuration

EEPROM, SMBus or internal ROM default setting. The state is only modified during a power on reset,

or hardware reset. No dynamic reconfiguring of this capability is possible.

Table 8.3 LPM State Definitions

STATE

DESCRIPTION

ENTRY/EXIT TIME TO L0

Suspend

Entry: ~3 ms

Exit: ~2 ms

Sleep

Entry: ~65 us

Exit: ~100 us

Fully Enabled (On)

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