USB2642 datasheet(4/56 Pages) MICROCHIP

4 / 56 page

 2014-2015 Microchip Technology Inc.

DS00001578C-page 4

USB2642

1.0

OVERVIEW

1.1

Introduction

The USB2642 offers a USB 2.0 compliant, versatile, cost-effective and energy-efficient hi-speed hub controller with 2

downstream USB ports and an SD/MMC flash media card interface. The dedicated flash media reader is internally

attached to a 3rd downstream port of the hub as a USB compound device. This combo solution supports today’s popular

multi-format flash media card formats. The flash media interface can support sustained transfer rates exceeding 35 MB/

s if the media and host support those rates.

The USB2642 also provides I2C over USB. The I2C bridge allows for control of any I2C device operating at 50kHz clock.

The USB2642 will attach to an upstream port as either a full-speed or full-/hi-speed hub. The hub supports low-speed,

full-speed, and hi-speed (if operating as a full-/hi-speed hub) downstream devices on all of the enabled downstream

ports.

All required resistors on the USB ports are integrated into the hub. This includes all series termination resistors on D+

and D- pins and all required pull-down and pull-up resistors. The over-current sense inputs for the downstream facing

ports have internal pull-up resistors.

The USB2642 includes programmable features such as:

PortMap

which provides flexible port mapping and disable sequences. The downstream ports of a USB2642 hub can

be reordered or disabled in any sequence to support multiple platform designs with minimum effort. For any port that is

disabled, the USB2642 automatically reorders the remaining ports to

match the USB host controller’s port numbering scheme.

PortSwap

which adds per-port programmability to USB differential-pair

pin locations. PortSwap allows direct alignment of USB signals (D+/D-)

to connectors avoiding uneven trace length or crossing of the USB differ-

ential signals on the PCB.

PHYBoost

which enables four programmable levels of USB signal drive

strength in downstream port transceivers. PHYBoost attempts to restore

USB signal integrity. The diagram on the right shows an example of Hi-

Speed USB eye diagrams before (PHYBoost at 0%) and after (PHYBoost

at 12%) signal integrity restoration in a compromised system environ-

ment.

USB2642 数据表(PDF) 4 Page - Microchip Technology

USB2642 数据表(HTML) 4 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载