USB2642 datasheet(10/56 Pages) MICROCHIP

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USB2642

DS00001578C-page 10

 2014-2015 Microchip Technology Inc.

PRTCTL[3:2]

I/OD12PU USB Power Enable

As an output, these pins enables power downstream USB peripheral

devices. See Section 5.3, "Port Power Control" for diagram and usage

instructions.

As an input, when the power is enabled, these pins monitor the over-

current condition. When an over-current condition is detected, these pins

turn the power off.

VBUS_DET

Detect Upstream VBUS Power

The Microchip hub monitors VBUS_DET to determine when to assert the

internal D+ pull-up resistor (signaling a connect event).

When designing a detachable hub, connect this pin to the VBUS power

pin of the USB port that is upstream of the hub.

For self-powered applications with a permanently attached host, this pin

should be pulled up, typically to VDD33.

VBUS is a 3.3 volt input. A resistor divider must be used when connecting

to 5 volts of USB power.

RBIAS

I-R

USB Transceiver Bias

A 12.0 kΩ,

±1.0% resistor is attached from VSS to this pin in order to set

the transceiver's internal bias currents.

XTAL1 (CLKIN)

ICLKx

24 MHz Crystal Input/External Clock Input

This pin can be connected to one terminal of the crystal or it can be

connected to an external 24 MHz clock when a crystal is not used.

XTAL2

OCLKx

24 MHz Crystal Output

This is the other terminal of the crystal, or a no connect pin, when an

external clock source is used to drive XTAL1 (CLKIN).

VDD18PLL

1.8 V PLL Power Bypass

This pin is the 1.8 V power bypass for the PLL. This pin requires an

external bypass capacitor of 1.0 µF.

If REG_EN is low, this pin serves as a power supply (1.8 V) for the device.

VDDA33

3.3 V Analog Power

• 48QFN - Pin 48 requires an external bypass capacitor of 4.7 µF.

SPI Interface

SPI_CE_N

O12

SPI Chip Enable

This is the active low chip enable output. If the SPI interface is enabled,

drive this pin high in power down states.

SPI_CLK/

I/O12

SPI Clock

This is the SPI clock out to the serial ROM. See Section 5.4, "ROM Boot

Sequence" for diagram and usage instructions.

During reset, this pin is driven low.

SCL_EP

When configured, this is the I²C EEPROM clock pin.

TABLE 5-1:

USB2642 PIN DESCRIPTIONS

Symbol

48-Pin

QFN

Buffer

Type

Description

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