LAN9500AI datasheet(12/213 Pages) MICROCHIP

12 / 213 page

LAN950x

DS00001875A-page 12

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TABLE 3-1:

MII INTERFACE PINS

Num Pins

Name

Symbol

Buffer

Type

Description

Receive Error

(Internal PHY

Mode)

RXER

IS/O8

(PD)

In internal PHY mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 122 for additional information.

Receive Error

(External PHY

Mode)

RXER

(PD)

In external PHY mode, the signal on this pin is

input from the external PHY and indicates a

receive error in the packet.

Transmit

Enable

(Internal PHY

Mode)

TXEN

IS/O8

(PD)

In internal PHY mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 122 for additional information.

Transmit

Enable

(External PHY

Mode)

TXEN

(PD)

In external PHY mode, this pin functions as an

output to the external PHY and indicates valid data

on TXD[3:0].

Receive Data

Valid

(Internal PHY

Mode)

RXDV

IS/O8

(PD)

In internal PHY mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 122 for additional information.

Receive Data

Valid

(External PHY

Mode)

RXDV

(PD)

In external PHY mode, the signal on this pin is

input from the external PHY and indicates valid

data on RXD[3:0].

Receive Clock

(Internal PHY

Mode)

RXCLK

IS/O8

(PD)

In internal PHY mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 122 for additional information.

Receive Clock

(External PHY

Mode)

RXCLK

(PD)

In external PHY mode, this pin is the receiver clock

input from the external PHY.

Carrier Sense

(Internal PHY

Mode)

CRS

IS/O8

(PU)

In internal PHY mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 122 for additional information.

Carrier Sense

(External PHY

Mode)

CRS

(PD)

In external PHY mode, the signal on this pin is

input from the external PHY and indicates a

network carrier.

General

Purpose I/O 3

(Internal PHY

Mode Only)

GPIO3

IS/O8/

OD8

(PU)

This General Purpose I/O pin is fully

programmable as either a push-pull output, an

open-drain output, or a Schmitt-triggered input.

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