LAN9500AI datasheet(124/213 Pages) MICROCHIP

124 / 213 page

LAN950x

DS00001875A-page 124

 2010 - 2015 Microchip Technology Inc.

Note 7-6

The default value of this bit depends on whether a NetDetach event occurred. If set, the event

occurred.

Note 7-7

The default value of this field is determined by the value of the PHY Boost field of the Configuration

Flags contained within the EEPROM, if present. If no EEPROM is present, 00b is the default. A USB

Reset or Lite Reset (LRST) will cause this field to be restored to the image value last loaded from

EEPROM, or to be set to 00b if no EEPROM is present.

Note 7-8

The PHY_SEL pin determines the default value.

Burst Cap Enable (BCE)

This register enables use of the burst cap register, Section 7.3.14, "Burst Cap

0 = Burst Cap register is not used to limit the TX burst size.

1 = Burst Cap register is used to limit the TX burst size.

R/W

Soft Reset (SRST)

Writing 1 generates a software initiated reset of the device. If an external

Ethernet PHY is used, it will be reset as well.

A software reset will result in the contents of the EEPROM being reloaded.

While the reset sequence is in progress, the USB PHY will be disconnected.

After the device has been reinitialized, it will take the PHY out of the

disconnect state and be visible to the Host.

Bits

Description

Type

Default

LAN9500AI 数据表(PDF) 124 Page - Microchip Technology