LAN9500AI datasheet(163/213 Pages) MICROCHIP

163 / 213 page

 2010 - 2015 Microchip Technology Inc.

DS00001875A-page 163

LAN950x

7.4.3

MAC ADDRESS LOW REGISTER (ADDRL)

This register contains the lower 32 bits of the physical address of the MAC, where ADDRL[7:0] is the first octet of the

Ethernet frame.

Table 7-5 illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the Ethernet

physical address.

As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and ADDRH registers would

be programmed as shown in Figure 7-1.

Address:

108h

Size:

32 bits

Note:

(LAN9500A/LAN9500Ai ONLY):

This register is protected by Reset Protection (RST_PROTECT).

Bits

Description

Type

Default

31:0

Physical Address [31:0]

This field contains the lower 32 bits (32:0) of the Physical Address of this

MAC device.

R/W

FFFF_FFFFh

TABLE 7-5:

ADDRL, ADDRH BYTE ORDERING

ADDRL, ADDRH

Order of Reception on Ethernet

ADDRL[7:0]

1st

ADDRL[15:8]

2nd

ADDRL[23:16]

3rd

ADDRL[31:24]

4th

ADDRH[7:0]

5th

ADDRH[15:8]

6th

FIGURE 7-1:

EXAMPLE ADDRL, ADDRH ADDRESS ORDERING

0x12

0x34

0x56

0x78

ADDRL

0x9A

0xBC

ADDRH

LAN9500AI 数据表(PDF) 163 Page - Microchip Technology

LAN9500AI 数据表(HTML) 163 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载