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DS00001979A-page 13

USB224X

6.0

PIN DESCRIPTIONS

This section provides a detailed description of each signal. The signals are arranged in functional groups according to

their associated interface. The pin descriptions are applied when using the internal default firmware and can be refer-

enced in Section 7.0, "Pin Configurations," on page 18. Please reference Section 2.0, "Acronyms," on page 4 for a list

of the acronyms used.

The “n” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage

level. When “n” is not present in the signal name, the signal is asserted at the high voltage level.

The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of

“active low” and “active high” signals. The term assert, or assertion, indicates that a signal is active, independent of

whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inac-

tive.

6.1

USB224x 36-Pin QFN Pin Descriptions

TABLE 6-1:

USB224X 36-PIN QFN PIN DESCRIPTIONS

Symbol

Buffer

Type

Description

xD-PICTURE CARD (xD) INTERFACE (APPLIES ONLY TO USB2240/USB2240I)

xD_D[7:0]

20

23

25

30

4

5

7

8

I/O12PD

xD Data

These bi-directional data signals have weak internal pull-

down resistors.

xD_nWP

9

O12PD

xD Write Protect

This pin is an active low write protect signal for the xD

device and has a weak pull-down resistor that is

permanently enabled.

xD_ALE

10

O12PD

xD Address Strobe

This pin is an active high Address Latch Enable signal for

the xD device and has a weak pull-down resistor that is

permanently enabled.

xD_CLE

11

O12PD

xD Command Strobe

This pin is an active high Command Latch Enable signal

for the xD device and has a weak pull-down resistor that

is permanently enabled.

xD_nRE

16

O12PU

xD Read Enable

This pin is an active low read strobe signal for the xD

device.

When using the internal FET, this pin has a weak internal

pull-up resistor that is tied to the output of the internal

power FET.

If an external FET is used (Internal FET is disabled), then

the internal pull-up is not available (external pull-ups must

be used).