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L2G3IS

Register description

26

7.9

CTRL_REG5 (1Fh)

To enable writing to the CTRL_REG5 (1Fh) register, the REG_EN bit in CTRL_REG1 (0Bh)

has to be set to ‘1’.

Table 24. CTRL_REG4 description

DRDY_EN

Data ready enable on DRDY pin. Default 0.

(1: DRDY on pin). Refer to Section 2.3: Synchronous reading.

Table 25. CTRL_REG5 register

--

--

--

--

FS

LPF2

HPF_BW1

HPF_BW0

Table 26. CTRL_REG5 description

FS

Full-scale selection. Default value: 0

(0: ±65 dps; 1: ±130 dps)

LPF2

Enable low-pass filter 240 Hz. Default 0.

If LPF2 is enabled, the cutoff frequency is set to 240 Hz, independently of the

value of the LPF bit in CTRL_REG3 (0Dh).

Refer to Table 19: Low-pass filter cutoff frequency.

HPF_BW[1:0]

Digital high-pass filter cutoff frequency selection. Default value 00.

Refer to Table 27: High-pass filter cutoff frequency selection

Table 27. High-pass filter cutoff frequency selection

HPF_BW1

HPF_BW0

HP cutoff frequency selection

0

0

0.02 Hz

0

1

0.08 Hz

1

0

4.85 Hz

1

1

39.6 Hz