Digital blocks

LED2472G

18/39

DocID024620 Rev 3

8

Digital blocks

The data inputs come in through the serial interface at each CLK rising edge and after 24

CLK cycles all data are loaded into the shift register. The LE signal is used to latch the

loaded data and also to generate digital keys for CFG management, scrolling, thermal check

and LED error detection. When one of the output enable signal (OER, OEB or OEG) is low,

the corresponding data are transferred to the relative output drivers. The data flow is “first in,

first out”. To latch the data, the LE signal must be high during the last data loading CLK

rising edge (Table 7). When one of the output enable signals (OER, OEB or OEG) is at low

level, output terminals (R1-R8,G1-G8, B1-B8) respond to the data either ON or OFF. When

one of the output enable signals (OER, OEB or OEG) goes to “1”, all outputs switch off all

the data on the output terminal. LE and /OE signals are asynchronous with respect to the

CLK signal. The time diagram below refers to RGB flow setting.

Figure 8. Data input time diagram

8.1

Register access

Access to the different registers of the device (configuration register, gain register, etc.) is

achieved by using different digital keys, defined as a number of CLK pulses during which the

LE signal is asserted. The available digital keys are summarized in Table 7.