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STC3117

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7

7.1

Read and write operations

data line (SDA) and a serial clock line (SCL).

•

SCL: input clock used to shift data

•

SDA: input/output bidirectional data transfers

A filter rejects the potential spikes on the bus data line to preserve data integrity.

The bidirectional data line supports transfers up to 400 Kbit/s (fast mode). The data are

shifted to and from the chip on the SDA line, MSB first.

The first bit must be high (START) followed by the 7-bit device address and the read/write

control bit. The default device address value is 1110 000. The STC3117 then sends an

acknowledge at the end of an 8-bit long sequence. The next eight bits correspond to the

register address followed by another acknowledge.

The data field is the last 8-bit long sequence sent, followed by a final acknowledge.

Figure 11. Read operation

Table 8. Device address format

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

111

000

0

R/W

Table 9. Register address format

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

RegADDR7

RegADDR6

RegADDR5

RegADDR4

RegADDR3

RegADDR2

RegADDR1

RegADDR0

Table 10. Register data format

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0