TUSB4041I

SLLSEK3B – JULY 2015 – REVISED DECEMBER 2015

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8.3.7 Power-Up and Reset

The TUSB4041I device does not have specific power-sequencing requirements with respect to the core power

indefinite period of time while the other is not powered up if all of the following constraints are met:

•

Observe all maximum ratings and recommended operating conditions.

•

Observe all warnings about exposure to maximum rated and recommended conditions, particularly junction

temperature. These apply to power transitions and normal operation.

•

•

powered-down.

A supply bus is powered-up when the voltage is within the recommended operating range. A supply bus is

powered-down when it is below that range, and either stable or in transition.

The device requires a minimum reset duration of 3 ms. This reset duration is defined as the time when the power

supplies are in the recommended operating range to the deassertion of the GRSTz pin. Generate the reset pulse

using a programmable-delay supervisory device or using an RC circuit.

8.4 Device Functional Modes

8.4.1 External Configuration Interface

The TUSB4041I device supports a serial interface for configuration register access. The device can be

external interface is enabled when both the SCL/SMBCLK and SDA/SMBDAT pins are pulled up to 3.3 V at the

EEPROM at bus address 1010000b using 7-bit addressing starting at address 0.

If the value of the EEPROM contents at byte 00h equals 55h, the TUSB4041I device loads the configuration

and continues execution with the default values in the configuration registers. The hub does not connect on the

upstream port until the configuration is completed. If the hub detected an unprogrammed EEPROM (value other

than 55h), the hub enters programming mode and a programming endpoint within the hub is enabled.

NOTE

The bytes located above offset Ah are optional. The requirement for data in those

addresses is dependent on the options configured in the Device Configuration Register

and Device Configuration Register 2.

8.4.3 SMBus Slave Operation

When the SMBus interface mode is enabled, the TUSB4041I device supports read block and write block

protocols as a slave-only SMBus device.

The TUSB4041I device slave address is 1000 1xyz, where:

•

x is the state of GANGED/SMBA2/HS_UP pin at reset

•

y is the state of FULLPWRMGMTz/SMBA1 pin at reset

•

z is the read-write (R/W) bit; 1 = read access, 0 = write access

If the TUSB4041I device is addressed by a host using an unsupported protocol, the device does not respond.

The TUSB4041I device waits indefinitely for configuration by the SMBus host and does not connect on the

upstream port until the SMBus host indicates configuration is complete by clearing the CFG_ACTIVE bit.

For details on SMBus requirements, refer to the System Management Bus (SMBus) Specification.

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