STAP16DPS05 datasheet(23/34 Pages) STMICROELECTRONICS

23 / 34 page

DocID024315 Rev 6

23/34

STAP16DPS05

Detection mode functionality

Figure 19. Error detection sequence

Typical schematic used to perform the error detection:

Figure 20. Error detection typical schematic

IODEC can be measured as follows:

IODEC = (Vled-Vload) / Rload

Table 14 and Table 15 show respectively the IODEC average value at 3.3 V and 5.0 V.

The IODEC is the current value recognized by the device output open error detection.

LE/DM1 and OE/DM2

Key Sequence

necessary to Enter

in EDM

16 CLK pulse are required to

load the data setting 1 into

shift register

The LE/DM1 pulse

latch the data

loaded during the

previous state

During the error

detection are

necessary at least

2 CLK signal plus

oneat the end

Every CLK pulse shows the results of

single Output results:Out15;14; 13 etc. etc

After OE/DM2 signal turn High the

the device from

EDM to Normal

Mode

16 CLK pulse are required to

load the data setting 1 into

shift register

During the error

detection are

necessary at least

2 CLK signal plus

oneat the end

Every CLK pulse shows the results of

single Output results:Out15;14; 13 etc. etc

SDO pin show the results of

Error Detection (Open or

Short in this case)

The OE/DM2 Pulse put

the device from

EDM to Normal

Mode

AM13678v1

DUT

Vled

Rload

IDEC

Out

REXT

Iset

Vdd

GND

STAP16DPS05 数据表(PDF) 23 Page - STMicroelectronics

STAP16DPS05 数据表(HTML) 23 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

数据表下载