SN74LVC1G97DBVT datasheet(12/33 Pages) TI1

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Time (ns)

Vin

Vout

C001

SN74LVC1G97

SCES416M – DECEMBER 2002 – REVISED JUNE 2015

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Typical Application (continued)

9.2.2 Detailed Design Procedure

The SN74LVC1G97 device uses CMOS technology and has balanced output drive. Avoid bus contentions

that can drive currents that can exceed maximum limits.

The SN74LVC1G97 allows for performing logical Boolean functions with digital signals. Maintain input signals

as close as possible to either 0 V or VCC for optimal operation.

9.2.3 Application Curve

VCC = 5 V

Figure 12. Simulated Input-to-Output Voltage Response Showing Propagation Delay

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the

Recommended Operating Conditions table.

To prevent power disturbance, ensure good bypass capacitance for each VCC terminal. For devices with a single-

supply, a 0.1-

μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF

capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual

supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended

for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors

with values of 0.1

μF and 1 μF are commonly used in parallel. Place the bypass capacitor as close to the power

terminal as possible for best results.

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