Final Datasheet TLE 6263

Version 2.08

30

2004-06-07

Pull down current at pin DI

and CLK

I

ICLK/DI

525

100

µA

Input capacitance

at pin CSN, DI or CLK

C

I

–10

15

pF

Not subject to

production test -

specified by design

Logic Output DO

H-output voltage level

V

DOH

V

CC

– 1.0

V

CC

– 0.7

–V

L-output voltage level

V

DOL

–

0.2

0.4

V

Tri-state leakage current

I

DOLK

– 10

–

10

µA

Tri-state input capacitance

C

DO

–10

15

pF

Not subject to

production test -

specified by design

Data Input Timing

Not subject to production test - specified by design

Clock period

t

pCLK

1000

–

–

ns

–

Clock high time

t

CLKH

500

–

–

ns

–

Clock low time

t

CLKL

500

–

–

ns

–

Clock low before CSN low

t

bef

500

–

–

ns

–

CSN setup time

t

lead

500

–

–

ns

–

CLK setup time

t

lag

500

–

–

ns

–

Clock low after CSN high

t

beh

500

–

–

ns

–

DI setup time

t

DISU

250

–

–

ns

–

DI hold time

t

DIHO

250

–

–

ns

–

Input signal rise time

at pin DI, CLK and CSN

t

rIN

–

–200

ns

–

Input signal fall time

at pin DI, CLK and CSN

t

fIN

–

–200

ns

–

7.3

Electrical Characteristics (cont’d)

characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise

specified.

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.