2

36-00-00-000

Ver. 1.3.1

Aeroflex Microelectronics Solutions - HiRel

1.0 Introduction

The UT700 LEON 3FT processor is based upon the industry-standard SPARC V8 architecture. The system-on-chip incorporates the

SPARC V8 core and the peripheral blocks indicated below. The core and peripherals communicate internally via the AMBA

(Advanced Microcontroller Bus Architecture) interconnect. This bus is comprised of the AHB (Advanced High-speed Bus) which is

used for high-speed data transfer, and the APB (Advanced Peripheral Bus) which is used for low-speed data transfer.

Figure 1. UT700 Functional Block Diagram

The LEON 3FT architecture includes the following peripheral blocks:

•

LEON3 SPARC V8 integer unit with 16kB instruction cache and 16kB of data cache

•

IEEE-754 floating point unit

•

Debug support unit

•

UART, JTAG, SpaceWire, PCI, and Ethernet debug links

•

8/16/32-bit memory controller with BCH EDAC for external PROM and SRAM

•

32-bit SDRAM controller with Reed Solomon EDAC for external SDRAM

•

Timer unit with three 32-bit timers and watchdog

•

Interrupt controller for 15 interrupts in two priority levels

•

16-bit general purpose I/O port (GPIO) which can be used as external interrupt sources

•

Up to four SpaceWire links with RMAP on all channels

•

MIL-STD-1553 interface supports BC/RT/MT

•

Up to two CAN controllers

•

Ethernet with support for MII

•

cPCI interface with 8-channel arbiter

Debug

Support

Unit

JTAG

Debug

Link

LEON 3FT

IEEE-754

FPU

MUL/DIV

MMU

4x4kB

Data Cache

4x4kB

Instr Cache

AHB Interface

SpW w/

RMAP

(4)

PCI

Bridge

Ethernet

MAC

CAN

(2)

SPI

MIL-

STD-

1553

AHB

Controller

AHB/APB

Bridge

FT Memory

Controller

APB

UART

Timers

(4)

INT

Ctrl

GPIO

Clock

Gating

512MB

PROM

256MB

I/O

Up to

1GB

SRAM

Up to

1GB

SDRAM

AMBA AHB

AMBA APB