3

FUNCTIONAL DESCRIPTION

The UT54ACTS899 has three principal modes of operation

which are outlined below. These modes apply to both A-to-B

and B-to-A directions.

- Bus A (B) communicates to Bus B (A), parity is generated

and passed on to the B (A) Bus as BPAR (APAR). If LEB

(LEA) is HIGH and the Mode Select (SEL) is LOW, the parity

generated from B[0:7] (A[0:7]) can be checked and moni-

tored by ERRB (ERRA).

FUNCTIONAL TABLE

- Bus A (B) communicates to Bus B (A) in a feed-through mode

if SEL is HIGH. Parity is still generated and checked as

ERRA and ERRB in the feed-through mode (can be used as

an interrupt to signal a data/parity bit error to the CPU).

- Independent Latch Enables (LEA and LEB) allow other per-

mutations of generating/checking. (see Function Table below)

H = High voltage level

L = Low voltage level

X = Do not care

Note 1: O/E = ODD/EVEN

INPUTS

GAB

GBA

SEL

LEA

LEB

H

H

X

X

X

Busses A and B are Tri-State (input A & B simultaneously)

H

L

L

L

H

Generates parity from B[0:7] based on O/E (Note 1). Generated parity --> APAR.

Generated parity checked against BPAR and output as ERRB.

H

L

L

H

H

Generates parity from B[0:7] based on O/E. Generated parity --> APAR.

Generated parity checked against BPAR and output as ERRB.

Generated parity also fed back through the A latch for generate/check as ERRA.

H

L

L

X

L

Generates parity from B latch data based on O/E. Generated parity --> APAR.

Generated parity checked against latched BPAR and output as ERRB.

H

L

H

X

H

BPAR/B[0:7] --> APAR/A[0:7] Feed-through mode.

Generated parity checked against BPAR and output as ERRB.

H

L

H

H

H

BPAR/B[0:7] --> APAR/A[0:7] Feed-through mode.

Generated parity checked against BPAR and output as ERRB.

APAR/A[0:7] fed back through the A latch for generate/check as ERRA.

L

H

L

H

L

Generates parity from A[0:7] based on O/E. Generated parity --> BPAR.

Generated parity checked against APAR and output as ERRA.

L

H

L

H

H

Generates parity from A[0:7] based on O/E. Generated parity --> BPAR.

Generated parity checked against APAR and output as ERRA.

Generated parity also fed back through the B latch for generate/check as ERRB.

L

H

L

L

X

Generates parity from A latch data based on O/E. Generated parity --> BPAR.

Generated parity checked against latched APAR and output as ERRA.

L

H

H

H

L

APAR/A[0:7)]--> BPAR/B[0:7] Feed-through mode.

Generated parity checked against APAR and output as ERRA.

L

H

H

H

H

APAR/A[0:7] --> BPAR/B[0:7] Feed-through mode.

Generated parity checked against APAR and output as ERRA.

BPAR/B[0:7] fed back through the B latch for generate/check as ERRB.

L

L

X

X

X

Output to A bus and B bus (NOT ALLOWED).