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Standard Products

UT54ACTS899

9-bit Latchable Transceiver with Parity Generator/Checker

Datasheet

May 16, 2012

www.aeroflex.com/Logic

FEATURES

 Latchable transceiver with output source/sink of 24mA

 Option to select generate parity and check or "feed-through"

data/parity in directions A-to-B or B-to-A

 Independent latch enable for A-to-B and B-to-A directions

 Select pin for ODD/EVEN parity

 ERRA and ERRB output pins for parity checking

 Ability to simultaneously generate and check parity



m Commercial CMOS

 Operational environment:

- Total dose: 100K rad(Si)

- Single Event Latchup immune

- SEU immune

 Standard Microcircuit Drawing 5962-06240

- QML compliant part

 Package:

- 28-pin ceramic flatpack

DESCRIPTION

The UT54ACTS899 is a 9-bit to 9-bit parity transceiver with

transparent latches. The device can operate as a feed-through

transceiver or it can generate/check parity from the 8-bit data

busses in either direction. The UT54ACTS899 features inde-

pendent latch enables for the A-to-B direction and the B-to-A

direction, a select pin for ODD/EVEN parity, and separate

error signal output pins for checking parity.

PIN DESCRIPTION

Inputs

Outputs

A0-A7

A Bus Data Inputs/Data Outputs

B0-B7

B Bus Data Inputs/Data Outputs

APAR, BPAR

A and B Bus Parity Inputs

ODD/EVEN

ODD/EVEN Parity Select, Active LOW for

EVEN Parity

GBA, GAB

Output Enables for A or B Bus, Active Low

SEL

Select Pin for Feed-through or Generate

Mode, LOW for Generate Mode

LEA, LEB

Latch Enables for A and B Latches, HIGH

for Transparent Mode

ERRA, ERRB

Error Signals for Checking Generated Par-

ity with Parity In, LOW if Error Occurs

28-Lead Flatpack

Pinout

1

2

3

4

5

7

6

28

27

26

25

24

22

23

ODD/EVEN

ERRA

LEA

A0

A1

A2

A3

VDD

GAB

B0

B1

B2

B4

8

21

A4

B5

B3

9

20

A5

B6

10

19

A6

B7

A7

APAR

GBA

VSS

11

12

13

14

18

17

16

15

BPAR

LEB

SEL

ERRB