54FCT533

General Description

The FCT533 consists of eight latches with TRI-STATE out-

puts for bus organized system applications. The flip-flops ap-

pear transparent to the data when Latch Enable (LE) is

HIGH. When LE is low, the data satisfying the input timing re-

quirements is latched. Data appears on the bus when the

Output Enable (OE) is LOW. When OE is HIGH, the bus out-

put is in the high impedance state.

Features

n Eight latches in a single package

n TTL input and output level compatible

n CMOS power consumption

n TRI-STATE outputs drive bus lines or buffer memory

address registers

n Output sink capability of 32mA, source capability of 12

mA

n Inverted version of the FCT373

n Standard Microcircuit Drawing (SMD) 5962-8865101

Logic Symbols

Pin

Names

Description

D

Data Inputs

LE

Latch Enable Input

OE

Output Enable Input

O

TRI-STATE Latch

Outputs

DS100969-1

IEEE/IEC

DS100969-2

September 1998

© 1998 National Semiconductor Corporation

DS100969

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