Silicon Image, Inc.

Silicon Image, Inc.

6

Subject to Change without Notice

AC Specifications (continued)

Under normal operating conditions unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

ODCK Cycle Time

1

(1-pixel/clock)

6.06

40

ns

ODCK Frequency

1

(1-pixel/clock)

25

165

MHz

ODCK Cycle Time

1

(2-pixels/clock)

12.1

80

ns

ODCK Frequency

1

(2-pixels/clock)

12.5

82.5

MHz

ODCK High Time

4

(165MHz, 1-pixel/clock, PIXS = 0)

ST = 1

1.7

ns

ST = 0

1.3

ns

ODCK Low Time

4

(165MHz, 1-pixel/clock, PIXS = 0)

ST = 1

2.0

ns

ST = 0

1.4

ns

Delay from PD Low to high impedance outputs

1

10

ns

Link disabled (DE inactive) to SCDT low

1

100

ms

Link disabled (Tx power down) to SCDT low

5

250

ms

Link enabled (DE active) to SCDT high

1

25

40

DE

edges

ODCK high to even data output

1

0.25

Notes:

1

Guaranteed by design.

2

Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification.

3

Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Pr ocedures.

4

Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.

5

Measured when transmitter was powered down (see Si

I/AN-0005 “PanelLink Basic Design/Application Guide,” Section 2.4).

Setup and Hold Timings for data rates other than 165 MHz:

The measurements shown above are minimum setup and hold timings based on the maximum data rate of 165 MHz.

To estimate the setup and hold times for slower data rates (for either different resolutions or 2 pixel per clock mode),

the following formula can be used:

Time (at new frequency) = Time (165 MHz) + (Clock Period at new frequency – Clock Period at 165 MHz)/2

For the case of high strength output (ST=1) with a 10 pf load, and using the standard ODCK (ODCK_INV = 0), the

table below shows the minimum set up and hold times for other speeds as follows:

Data Rate (MHz)

Clock (ns) Setup (ns) Hold (ns)

165

6.06

0.70

3.80

UXGA 1 pixel/clock

112

8.93

2.13

5.23

SXGA 1 pixel/clock

82.5

12.12

3.73

6.83

UXGA 2 pixels/clock

56

17.86

6.60

9.70

SXGA 2 pixels/clock