Silicon Image, Inc.

Silicon Image, Inc.

13

Subject to Change without Notice

TFT Panel Data Mapping

The following table shows the output data mapping in one pixel per clock mode for the Si

I 161A. This output data

mapping is dependent upon the

Please refer to the Si

I PanelLink transmitter for the specific input data mappings and to the TFT Signal Mapping

application note (Si

I AN-0007).

Si

1-Pixel/Clock Output

18bpp

24bpp

BLUE[7:0]

QE[7:2]

QE[7:0]

GREEN[7:0]

QE[15:10]

QE[15:8]

RED[7:0]

QE[23:18]

QE[23:16]

Table 1. One Pixel/Clock Mode Data Mapping

Si

2-Pixel/Clock Output

18bpp

24bpp

BLUE[7:0] - 0

QE[7:2]

QE[7:0]

GREEN[7:0] – 0

QE[15:10]

QE[15:8]

RED[7:0] – 0

QE[23:18]

QE[23:16]

BLUE[7:0] – 1

QO[7:2]

QO[7:0]

GREEN[7:0] – 1

QO[15:10]

QO[15:8]

RED[7:0] – 1

QO[23:18]

QO[23:16]

Table 2. Two Pixel/Clock Mode Data Mapping

Note: For 18-bit mode, the Flat Panel Timing Controller interfaces to the Si

mode; however, only 6-bits per channel (color) are interfaced instead of the full 8. As can be seen from the above

table, the data mapping for less than 24-bit per pixel interfaces are MSB justified.