LP5520 datasheet(7/46 Pages) TI1

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Data

BIT 1

LSB IN

LSB OUT

BIT 1

MSB OUT

BIT 7

BIT 8

BIT 9

BIT 14

MSB IN

R/W

Address

SDA

SCL

LP5520

www.ti.com

SNVS440B – MAY 2007 – REVISED MARCH 2016

Product Folder Links: LP5520

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6.9 I

2C Timing Parameters

VDD1,2 = 3 V to 4.5 V, VDDIO = 1.8 V To VDD1,2; see Figure 1.

MIN

MAX

UNIT

Hold time (repeated) START condition

0.6

µs

Clock low time

1.3

µs

Clock high time

600

Setup time for a repeated START condition

600

Data hold time (output direction, delay generated by LP5520)

300

900

Data hold time (input direction, delay generated by Master)

900

Data setup time

100

Rise time of SDA and SCL

20 + 0.1Cb

300

Fall time of SDA and SCL

15 + 0.1Cb

300

Setup time for STOP condition

600

Bus free time between a STOP and a START condition

1.3

µs

Capacitive load for each bus line

200

6.10 SPI Timing Requirements

See Figure 2.

MIN

MAX

UNIT

Cycle time

Enable lead time

Enable lag time

Clock low time

Clock high time

Data setup time

Data hold time

Data access time

Disable time

Data valid

Data hold time

Figure 1. I2C Timing Diagram

Figure 2. SPI Timing Diagram

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