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SWCS049F 数据表(PDF) 16 Page - Texas Instruments |
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SWCS049F 数据表(HTML) 16 Page - Texas Instruments |
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16 / 119 page  16 TPS659110, TPS659112, TPS659113 TPS659114, TPS659118, TPS6591133 SWCS049Q – JUNE 2010 – REVISED MARCH 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659114 TPS659118 TPS6591133 Specifications Copyright © 2010–2016, Texas Instruments Incorporated (1) The input timing requirements are given by considering a rising or falling time of 80 ns in high–speed mode (3.4 Mbps), 300 ns in fast–speed mode (400 kbps), 1000 ns in standard mode (100 kbps) (2) SDA is SDA_SDI or EN2 signal, SCL is SCL_SCK or EN1 signal 5.8 I 2C Interface and Control Signals over operating free-air temperature range (unless otherwise noted) NO. PARAMETER TEST CONDITIONS(1) (2) MIN TYP UNIT INT1 rise and fall times, CL = 5 to 35 pF 5 10 ns NRESPWRON rise and fall times, CL = 5 to 35 pF 5 10 ns SLAVE HIGH–SPEED MODE SCL/EN1 and SDA/EN2 rise and fall time, CL = 10 to 100 pF 10 80 ns Data rate 3.4 Mbps I3 tsu(SDA-SCLH) Setup time, SDA valid to SCL high 10 ns I4 th(SCLL-SDA) Hold time, SDA valid from SCL low 0 70 ns I7 tsu(SCLH-SDAL) Setup time, SCL high to SDA low 160 ns I8 th(SDAL-SCLL) Hold time, SCL low from SDA low 160 ns I9 tsu(SDAH-SCLH) Setup time, SDA high to SCL high 160 ns SLAVE FAST MODE SCL/EN1 and SDA/EN2 rise and fall time, CL = 10 to 400 pF 20 + 0.1 × CL 250 ns Data rate 400 Kbps I3 tsu(SDA-SCLH) Setup time, SDA valid to SCL high 100 ns I4 th(SCLL-SDA) Hold time, SDA valid from SCL low 0 0.9 µs I7 tsu(SCLH-SDAL) Setup time, SCL high to SDA low 0.6 µs I8 th(SDAL-SCLL) Hold time, SCL low from SDA low 0.6 µs I9 tsu(SDAH-SCLH) Setup time, SDA high to SCL high 0.6 µs SLAVE STANDARD MODE SCL/EN1 and SDA/EN2 rise and fall time, CL = 10 to 400 pF 250 ns Data rate 100 Kbps I3 tsu(SDA-SCLH) Setup time, SDA valid to SCL high 250 ns I4 th(SCLL-SDA) Hold time, SDA valid from SCL low 0 µs I7 tsu(SCLH-SDAL) Setup time, SCL high to SDA low 4.7 µs I8 th(SDAL-SCLL) Hold time, SCL low from SDA low 4 µs I9 tsu(SDAH-SCLH) Setup time, SDA high to SCL high 4 µs SWITCHING CHARACTERISTICS SLAVE HIGH–SPEED MODE I1 tw(SCLL) Pulse duration, SCL low 160 ns I2 tw(SCLH) Pulse duration, SCL high 60 ns SLAVE FAST MODE I1 tw(SCLL) Pulse duration, SCL low 1.3 µs I2 tw(SCLH) Pulse duration, SCL high 0.6 µs SLAVE STANDARD MODE I1 tw(SCLL) Pulse duration, SCL low 4.7 µs I2 tw(SCLH) Pulse duration, SCL high 4 µs |
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