SP6123 datasheet(13/18 Pages) SIPEX

13 / 18 page

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

fP(LC) =

π√ LCOUT

The open loop gain of the whole system can be

divided into the gain of the error amplifier,

PWM modulator, buck converter, and feedback

resistor divider. In order to crossover at the

selected frequency fco, the gain of the error

amplifier has to compensate for the attenuation

caused by the rest of the loop at this frequency.

In the RC network shown in Figure 1, the product

of R1 and the error amplifier transconductance

determines this gain. Therefore, R1 can be de-

termined from the following equation that takes

into account the typical error amplifier

transconductance, reference voltage and PWM

ramp built into the SP6123.

R1 =

2083VOUT fCO fZ(ESR)

VIN fP(LC)2

In Figure 1, R1 and C1 provides a zero fZ1 which

needs to be placed at or below fP(LC). If fZ1 is

made equal to fP(LC) for convenience, the value

of C1 can be calculated as

C1 =

πfP(LC)R1

The optional C2 generates a pole fP1 with R1 to

cut down high frequency noise for reliable op-

eration. This pole should be placed one decade

higher than the crossover frequency to avoid

erosion of phase margin. Therefore, the value of

the C2 can be derived from

C2 =

πfCOR1

Figure 2 illustrates the overall loop frequency

response and frequency of each pole and zero.

To fine-tune the compensation, it is necessary to

physically measure the frequency response us-

ing a network analyzer.

Gain

-20db/dec

-40db/dec

-20db/dec

Error Amplifier

Loop

fZ1 fP(LC) fZ(ESR)

fCO

fP1

Figure 2. Frequency response of a stable system and its

error amplifier.

MBR0530

BST

SWN

VCC

VFB

COMP

GND

5.0

20k

2.2µF

SP6123A

47pF

FDS6890A

CIN

47µF Ceramic

80k

1.6V/4A

CBST

1µF

1µH

COUT

4x47µF Ceramic

80k

330pF

STPS2L25U

680pF

3V to 5.5V

FDS6890A

Figure 3. SP6123 Buck converter design with ceramic output capacitors.

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