4

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

© Copyright 2004 Sipex Corporation

General Overview

The SP6123 is a constant frequency, voltage mode,

synchronous PWM controller designed for low

voltage, DC/DC step down converters. It is in-

tended to provide complete control for a high

power, high efficiency, precisely regulated output

voltage from a highly integrated 8-pin solution.

The internal free-running oscillator accurately sets

the PWM frequency at 300kHz or 500kHz without

requiring any external elements and allows the use

of physically small, low value external compo-

nents without compromising performance. A

transconductance amplifier is used for the error

amplifier, which compares an attenuated sample

of the output voltage with a precision, 0.8V refer-

ence voltage. The output of the error amplifier

(COMP), is compared to a 0.75V peak-to-peak

ramp waveform to provide PWM control. The

COMP pin provides access to the output of the

error amplifier and allows the use of external

components to stabilize the voltage loop.

High efficiency is obtained through the use of

synchronous rectification. Synchronous regula-

tors replace the catch diode in the standard buck

MOSFET switch allowing for significant effi-

ciency improvements. The SP6123 includes two

fast MOSFET drivers with internal non-overlap

circuitry and drives a pair of N-channel power

transistors. The SP6123 includes an internal

soft-start circuit that provides controlled ramp

up of the output voltage, preventing overshoot

and inrush current at power up.

Current limiting is implemented by monitoring

side N-channel MOSFET while it is conducting,

thereby eliminating the need for an external

sense resistor. The overcurrent comparator has

a built-in threshold of 200mV .

When the overcurrent threshold is exceeded, the

overcurrent comparator sets the fault latch and

terminates the output pulses. The controller

stops switching and goes through a hiccup se-

quence. This prevents excessive power dissipa-

tion in the external power MOSFETs during an

overload condition. An internal delay circuit

prevents that very short and mild overload con-

ditions, that could occur during a load transient,

activate the current limit circuit.

+

-

-

+

-

+

Synchronous

Driver

PWM

Logic

S

Q

R

Reset

Dominant

R

Q

S

SWN

Reference

4

5

0.8V

UVLO

FAULT

SWN

6

1

GL

7

DRIVER ENABLE

RESET

Dominant

PWM COMP

FAULT

+

-

X 2.5

GH

GH

5µA

350mV

SHUTDOWN

GM

ERROR

AMP

Over Current

(Gated S&H)

2.8V ON

2.7V OFF

COMP

SHUTDOWN

F = 300kHz; SP6123

F = 500kHz; SP6123A

750mV RAMP

SOFTSTART

COMP

2

-

+

-

+

1V

500mV

(4000 ppm/°C)

+

-

GND

3

8

BST

BLOCK DIAGRAM

OPERATION