2

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06/05/15

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PI6CFGL401B

4-Output Low Power PCIE Gen 1-2-3 Clock Generator

SMBus Address Selection Table

SADR Address + Read/Write Bit

State of SADR on first application

of CKPWRGD_PD#

0

1101000

1/0

1

1101010

1/0

Pin Configuration (32-Pin TQFN)

7

8

9 10 11 12 13 14 15 16

1

2

3

4

5

6

VDDXTAL

VDDREF1.8

GNDA

VDDA3.3

XTAL_OUT

XTAL_IN

GNDXTAL

OE2#

CLK2#

CLK2

18

17

24

23

22

21

20

19

32 31 30 29 28 27 26 25

GNDDIG

GNDREF

SADR/REF1.8

CLK1#

CLK1

OE1#

Power Connections

Pin Number

Description

VDD

GND

4

1

XTAL Analog

5

7

REF Output

9

8, 30

Digital Power

16, 25

15, 26

DIF outputs

21

20

PLL Analog

Power Management Table

CKPWRGD_PD#

SMBus OE bit

CLKx

REF1.8

True O/P

Comp. O/P

0

x

Low

Low

1

1

Running

Running

Running

1

0

Low

Low

Low

Note:

1. REF1.8 is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when CKPWRG_PD# is low, REF1.8 is Low.

CKPWRGD_PD#

OE (Pin)

OE (SMBus bit)

CLKx

True O/P

Comp. O/P

0

X

x

Low

Low

1

0

0

Low

Low

1

0

1

Running

Running

1

1

0

Low

Low

1

1

1

Low

Low

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