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06/05/15

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PI6CFGL401B

4-Output Low Power PCIE Gen 1-2-3 Clock Generator

Pin Description

Pin# Pin Name

Type

Description

1

GNDXTAL

Power

GND for XTAL

2

XTAL_IN

Input

Crystal input or Reference Clock input. Nominally 25MHz.

3

XTAL_OUT

Output

Crystal output.

4

VDDXTAL

Power

3.3 Power supply for XTAL.

5

VDDREF1.8

Power

VDD for REF output. nominal 1.8V.

6

SADR/REF1.8 Input/Output Latch to select SMBus Address/1.8V LVCMOS Ref output.

7

GNDREF

Power

Ground pin for the REF outputs.

8

GNDDIG

Power

Ground pin for digital circuitry.

9

VDDDIG3.3

Power

3.3V digital power (dirty power)

10

SCLK_3.3

Input

Clock pin of SMBus circuitry, 3.3V tolerant.

11

SDATA_3.3

Input/Output Data pin for SMBus circuitry, 3.3V tolerant.

12

OE0#

Input

Active low input for enabling DIF pair 0. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

13

CLK0

Output

Differential true clock output

14

CLK0#

Output

Differential Complementary clock output

15

GND

Power

Ground pin.

16

VDDO1.8

Power

Power supply for outputs, nominally 1.8V, range 1.05V~3.3V.

17

OE1#

Input

Active low input for enabling DIF pair 1. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

18

CLK1

Output

Differential true clock output

19

CLK1#

Output

Differential Complementary clock output

20

GNDA

Power

Ground pin for the PLL core.

21

VDDA3.3

Power

3.3V power for the PLL core.

22

CLK2

Output

Differential true clock output.

23

CLK2#

Output

Differential Complementary clock output.

24

OE2#

Input

Active low input for enabling DIF pair 2. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

25

VDDO1.8

Power

Power supply for outputs, nominally 1.8V, range 1.05V~3.3V.

26

GND

Power

Ground pin.

27

CLK3

Output

Differential true clock output

28

CLK3#

Output

Differential Complementary clock output

29

OE3#

Input

Active low input for enabling DIF pair 3. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

30

GND

Power

Ground pin.

31

CKPWRGD_

PD#

Input

Input notifies device to sample latched inputs and start up on first high assertion. Low

enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin

has internal pull-up resistor.

32

SS_EN_tri

Input

Latched select input to select spread spectrum amount at initial power up :

1 = -0.5% spread, M = -0.25%, 0 = Spread Off

15-0072