ADC0803 datasheet(4/41 Pages) NSC

4 / 41 page

AC Electrical Characteristics (Continued)

The following specifications apply for V

CC=5VDC and TMIN≤TA≤TMAX unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

OUT

TRI-STATE Output

7.5

Capacitance (Data Buffers)

CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]

IN (1)

Logical “1” Input Voltage

CC=5.25 VDC

2.0

(Except Pin 4 CLK IN)

IN (0)

Logical “0” Input Voltage

CC=4.75 VDC

0.8

(Except Pin 4 CLK IN)

IN (1)

Logical “1” Input Current

IN=5VDC

0.005

µA

(All Inputs)

IN (0)

Logical “0” Input Current

IN=0VDC

−1

−0.005

µA

(All Inputs)

CLOCK IN AND CLOCK R

T+

CLK IN (Pin 4) Positive Going

2.7

3.1

3.5

Threshold Voltage

T−

CLK IN (Pin 4) Negative

1.5

1.8

2.1

Going Threshold Voltage

CLK IN (Pin 4) Hysteresis

0.6

1.3

2.0

T+)−(VT−)

OUT (0)

Logical “0” CLK R Output

O=360 µA

0.4

Voltage

CC=4.75 VDC

OUT (1)

Logical “1” CLK R Output

O=−360 µA

2.4

Voltage

CC=4.75 VDC

DATA OUTPUTS AND INTR

OUT (0)

Logical “0” Output Voltage

Data Outputs

OUT=1.6 mA, VCC=4.75 VDC

0.4

INTR Output

OUT=1.0 mA, VCC=4.75 VDC

0.4

OUT (1)

Logical “1” Output Voltage

O=−360 µA, VCC=4.75 VDC

2.4

OUT (1)

Logical “1” Output Voltage

O=−10 µA, VCC=4.75 VDC

4.5

OUT

TRI-STATE Disabled Output

OUT=0VDC

−3

µA

Leakage (All Data Buffers)

OUT=5VDC

3µA

SOURCE

OUT Short to Gnd, TA=25˚C

4.5

SINK

OUT Short to VCC,TA=25˚C

9.0

POWER SUPPLY

Supply Current (Includes

CLK=640 kHz,

Ladder Current)

REF/2=NC, TA=25˚C

and CS =5V

ADC0801/02/03/04LCJ/05

1.1

1.8

ADC0804LCN/LCWM

1.9

2.5

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.

Note 3: A zener diode exists, internally, from VCC to Gnd and has a typical breakdown voltage of 7 VDC.

Note 4: For VIN(−)≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct

for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high

level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows

50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct.

To achieve an absolute 0 VDC to5VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance

and loading.

Note 5: Accuracy is guaranteed at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be ex-

tended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.

Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The

start request is internally latched, see

Figure 4 and section 2.0.

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