ADC1001 datasheet(3/9 Pages) NSC

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DC Electrical Characteristics

The following specifications apply for V

CC=5VDC and TMIN≤TA≤ TMAX, unless otherwise specified.

Symbol

Parameter

Conditions

MIn

Typ

Max

Units

CONTROL INPUTS [Note: CLK IN is the input of a Schmitt trigger circuit and is therefore specified separately]

IN (1)

Logical “1” Input Voltage

CC=5.25 VDC

2.0

(Except CLK IN)

IN (0)

Logical “0” Input Voltage

CC=4.75 VDC

0.8

(Except CLK IN)

IN (1)

Logical “1” Input Current

IN=5VDC

0.005

µA

(All Inputs)

IN (0)

Logical “0” input Current

IN=0VDC

−1

−0.005

µA

(All Inputs)

CLOCK IN

T+

CLK IN Positive Going

2.7

3.1

3.5

Threshold Voltage

T−

CLK IN Negative Going

1.5

1.8

2.1

Threshold Voltage

CLK IN Hysteresis

0.6

1.3

2.0

T+)−(VT−)

OUTPUTS AND INTR

OUT(0)

Logical “0” Output Voltage

OUT=1.6 mA, VCC=4.75 VDC

0.4

OUT(1)

Logical “1” Output Voltage

O=−360 µA, VCC=4.75 VDC

2.4

O=−10 µA, VCC=4.75 VDC

4.5

OUT

TRI-STATE Disabled Output

OUT=0.4 VDC

0.1

−100

µA

Leakage (All Data Buffers)

OUT=5VDC

0.1

µA

SOURCE

OUT Short to GND, TA=25˚C

4.5

SINK

OUT Short to VCC,TA=25˚C

9.0

POWER SUPPLY

Supply Current (Includes

CLK=410 kHz,

Ladder Current)

REF/2=NC, TA=25˚C

and CS =1

2.5

5.0

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified. The separate A GND point should always be wired to the D GND.

Note 3: A zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.

Note 4: For VIN(−)≥ VIN(+) the digital output code will be all zeros. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct

for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high

level analog inputs (5V) can cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near fullscale. The spec al-

lows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will

be correct. To achieve an absolute 0 VDC to5VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial

tolerance and loading.

Note 5: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The

start request is internally latched, see

Figure 3 .

Note 6: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold

the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see Timing Diagrams).

Note 7: All typical values are for TA=25˚C.

Note 8: Accuracy is guaranteed at fCLK=410 kHz. At higher clock frequencies accuracy can degrade.

Note 9: The VREF/2 pin is the center point of a two resistor divider (each resistor is 2.4kΩ) connected from VCC to ground. Total ladder input resistance is the sum

of these two equal resistors.

Note 10: Human body model, 100 pF discharged through a 1.5 k

Ω resistor.

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