TLH11490 – 16

FIGURE 6 ADC Control Logic

20 THE ANALOG INPUT

The analog input of the ADC12062 can be modeled as two

small resistances in series with the capacitance of the input

is closed during the Sample period and open during Hold

sample period Note that the source impedance of the input

conversion begins and the conversion results will be incor-

rect From a dynamic performance viewpoint the combina-

sponse of the input stage of the converter

Typical values for the components shown in

Figure 7 are

tling time to n bits is

The bandwidth of the input circuit is

For maximum performance the impedance of the source

driving the ADC12062 should be made as small as possible

A source impedance of 100X or less is recommended A

plot of dynamic performance vs source impedance is given

in the Typical Performance Characteristics section

If the signal source has a high output impedance its output

should be buffered with an operational amplifier capable of

driving a switched 25 pF100X load Any ringing or instabili-

ties at the op amp’s output during the sampling period can

result in conversion errors The LM6361 high speed op amp

is a good choice for this application due to its speed and its

ability to drive large capacitive loads

Figure 8 shows the

LM6361 driving the ADC IN input of an ADC12062 The

100 pF capacitor at the input of the converter absorbs some

of the high frequency transients generated by the SH

switching reducing the op amp transient response require-

ments The 100 pF capacitor should only be used with high

speed op amps that are unconditionally stable driving ca-

pacitive loads

TLH11490 – 17

FIGURE 7 Simplified ADC12062 Input Stage

12