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ADC12062 数据表(PDF) 15 Page - National Semiconductor (TI) |
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ADC12062 数据表(HTML) 15 Page - National Semiconductor (TI) |
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15 / 20 page ![]() Applications Information (Continued) Since the current flowing through the SENSE lines is essen- tially zero there is negligible voltage drop across RS and the 1kX resistor so the voltage at the inverting input of the op amp accurately represents the voltage at the top (or bot- tom) of the ladder The op amp drives the FORCE input and forces the voltage at the ends of the ladder to equal the voltage at the op amps’s non-inverting input plus or minus its input offset voltage For this reason op amps with low VOS such as the LM627 or LM607 should be used for this application When used in this configuration the ADC12062 typically has less than 05 LSB of offset and gain error with- out any user adjustments The 01 mF and 10 mF capacitors on the force inputs pro- vide high frequency decoupling of the reference ladder The 500X force resistors isolate the op amps from this large capacitive load The 001 mF1 kX network provides zero phase shift at high frequencies to ensure stability Note that the op amp supplies in this example must be g10V to g 15V to meet the inputoutput voltage range requirements of the LM627 and supply the sub-zero voltage to the VREFb (FORCE) pin The VREF16 output should be by- passed to analog ground with a 01 mF ceramic capacitor The reference inputs are fully differential and define the zero to full-scale range of the input signal They can be configured to span up to 5V (VREFb e 0V VREFa e 5V) or they can be connected to different voltages (within the 0V to 5V limits) when other input spans are required The ADC12062 is tested at VREFb (SENSE) e 0V VREFa (SENSE) e 4096V Reducing the reference voltage span to less than 4V increases the sensitivity (reduces the LSB size) of the converter however noise performance degrades when lower reference voltages are used A plot of dynamic performance vs reference voltage is given in the Typical Performance Characteristics section If the converter will be used in an application where DC accuracy is secondary to dynamic performance then a sim- pler reference circuit may suffice The circuit shown in Fig- ure 11 will introduce several LSBs of offset and gain error but INL DNL and all dynamic specifications will be unaf- fected All bypass capacitors should be located as close to the ADC12062 as possible to minimize noise on the reference ladder The VREF16 output should be bypassed to analog ground with a 01 mF ceramic capacitor The LM4040 shunt voltage reference is available with a 4096V output voltage With initial accuracies as low as g 01% it makes an excellent reference for the ADC12062 TLH11490 – 21 FIGURE 11 Using the VREF Force Pins Only 15 |
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