ADC12062EVAL datasheet(9/20 Pages) NSC

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Pin Descriptions

AVCC

These are the two positive analog supply

inputs They should always be connected

to the same voltage source

but are

brought out separately to allow for sepa-

rate bypass capacitors Each supply pin

should be bypassed to AGND with a

01 mF ceramic capacitor in parallel with a

10 mF tantalum capacitor

DVCC

This is the positive digital supply input It

should always be connected to the same

voltage as the analog supply AVCC It

should be bypassed to DGND2 with a

01 mF ceramic capacitor in parallel with a

10 mF tantalum capacitor

AGND

These are the power supply ground pins

DGND1

There are separate analog and digital

DGND2

ground pins for separate bypassing of the

analog and digital supplies The ground

pins should be connected to a stable

noise-free system ground

All of the

ground pins should be returned to the

same potential

AGND is the analog

ground for the converter DGND1 is the

ground pin for the digital control lines

DGND2 is the ground return for the output

databus See Section 60 LAYOUT AND

GROUNDING for more information

DB0 – DB11

These are the TRI-STATE output pins en-

abled by RD CS and OE

VIN1 VIN2

These are the analog input pins to the mul-

tiplexer For accurate conversions no in-

put pin (even one that is not selected)

should be driven more than 50 mV below

ground or 50 mV above VCC

MUX OUT

This is the output of the on-board analog

input multiplexer

ADC IN

This is the direct input to the 12-bit sam-

pling AD converter For accurate conver-

sions this pin should not be driven more

than 50 mV below AGND or 50 mV above

AVCC

This pin selects the analog input that will

be connected to the ADC12062 during the

conversion The input is selected based on

the state of S0 when EOC makes its high-

to-low transition Low selects VIN1 high

selects VIN2

MODE

This pin should be tied to DVCC

This is the active low Chip Select control

input When low this pin enables the RD

SH and OE inputs This pin can be tied

low

INT

This is the active low Interrupt output

When using the Interrupt Interface Mode

(Figure 1) this output goes low when a

conversion has been completed and indi-

cates that the conversion result is avail-

able in the output latches This output is

always high when RD is held low

(Figure

EOC

This is the End-of-Conversion control out-

put This output is low during a conversion

This is the active low Read control input

When RD is low (and CS is low) the INT

output is reset and (if OE is high) data ap-

pears on the data bus This pin can be tied

low

This is the active high Output Enable con-

trol input This pin can be thought of as an

inverted version of the RD input (see

Fig-

ure 6 ) Data output pins DB0 – DB11 are

TRI-STATE when OE is low Data appears

on DB0 – DB11 only when OE is high and

CS and RD are both low This pin can be

tied high

This is the SampleHold control input The

analog input signal is held and a new con-

version is initiated by the falling edge of

this control input (when CS is low)

This is the Power Down control input This

pin should be held high for normal opera-

tion When this pin is pulled low the device

goes into a low power standby mode

VREFa(FORCE) These are the positive and negative volt-

VREFb(FORCE) age reference force inputs respectively

See Section 4 REFERENCE INPUTS for

more information

VREFa(SENSE) These are the positive and negative volt-

VREFb(SENSE) age reference sense pins respectively

See Section 4 REFERENCE INPUTS for

more information

VREF 16

This pin should be bypassed to AGND with

a 01 mF ceramic capacitor

TEST

This pin should be tied to DVCC

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