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ADC12062EVAL 数据表(PDF) 3 Page - National Semiconductor (TI) |
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ADC12062EVAL 数据表(HTML) 3 Page - National Semiconductor (TI) |
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3 / 20 page ![]() DC Electrical Characteristics The following specifications apply for DV CC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF−(SENSE) = AGND, and fs = 1.4 MHz, unless otherwise specified. Boldface limits apply for T A = TJ from TMIN to TMAX; all other limits TA = TJ = +25˚C. Symbol Parameter Conditions Typ Limit Units (Note 7) (Note 8) (Limit) V IN(1) Logical “1” Input Voltage DV CC = AVCC = +5.5V 2.0 V (min) V IN(0) Logical “0” Input Voltage DV CC = AVCC = +4.5V 0.8 V (max) I IN(1) Logical “1” Input Current 0.1 1.0 µA (max) I IN(0) Logical “0” Input Current 0.1 1.0 µA (max) V OUT(1) Logical “1” Output Voltage DV CC = AVCC = +4.5V, I OUT = −360 µA 2.4 V (min) I OUT = −100 µA 4.25 V (min) V OUT(0) Logical “0” Output Voltage DV CC = AVCC = +4.5V, 0.4 V (max) I OUT = 1.6 mA I OUT TRI-STATE® Output Pins DB0–DB11 0.1 3 µA (max) Leakage Current C OUT TRI-STATE Output Capacitance Pins DB0–DB11 5 pF C IN Digital Input Capacitance 4 pF DI CC DV CC Supply Current 2 10 mA (max) AI CC AV CC Supply Current 32 50 mA (max) I STANDBY Standby Current (DI CC +AICC)PD = 0V 50 µA AC Electrical Characteristics The following specifications apply for DV CC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF−(SENSE) = AGND, and fs = 1.4 MHz, unless otherwise specified. Boldface limits apply for T A = TJ from TMIN to TMAX; all other limits TA = TJ = +25˚C. Symbol Parameter Conditions Typ Limit Units (Note 7) (Note 8) (Limits) f s Maximum Sampling Rate 1.5 MHz (min) (1/t THROUGHPUT) t CONV Conversion Time 593 560 ns (min) (S/H Low to EOC High) 710 ns (max) t AD Aperture Delay 20 ns (S/H Low to Input Voltage Held) t S/H S/H Pulse Width 10 5 ns (min) 400 ns (max) t EOC S/H Low to EOC Low 90 60 ns (min) 126 ns (max) t ACC Access Time C L = 100 pF 10 20 ns (max) (RD Low or OE High to Data Valid) t 1H,t0H TRI-STATE Control R L = 1k, CL = 10 pF 25 40 ns (max) (RD High or OE Low to Databus TRI-STATE) t INTH Delay from RD Low to INT High C L = 100 pF 35 60 ns (max) t INTL Delay from EOC High to INT Low C L = 100 pF −25 −35 ns (min) −10 ns (max) t UPDATE EOC High to New Data Valid 5 15 ns (max) t MS Multiplexer Address Setup Time 50 ns (min) (MUX Address Valid to EOC Low) t MH Multiplexer Address Hold Time 50 ns (min) (EOC Low to MUX Address Invalid) t CSS CS Setup Time 20 ns (min) (CS Low to RD Low, S/H Low, or OE High) www.national.com 3 |
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