Micro Crystal

Real Time Clock / Calendar Module

RV-8564

25/40

10.4.ACKNOWLEDGE

There is no limit to the numbers of data bytes transmitted between the START and STOP conditions. Each byte (of

8 bits) is followed by an acknowledge cycle. Therefore, the Master generates an extra acknowledge clock pulse.

The acknowledge bit is a HIGH level signal put on the SDA line by the Transmitter-Device, the Receiver-Device

must pull down the SDA line during the acknowledge clock pulse to confirm the correct reception of the last byte.

Either a Master-Receiver or a Slave-Receiver which is addressed must generate an acknowledge after the correct

reception of each byte. The device that acknowledges must pull-down the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (setup

and hold times must be taken into consideration).

If the Master is addressed as Receiver, it can stop data transmission by not generating an acknowledge on the last

byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the data line

HIGH to enable the Master to generate a STOP condition.