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AD7779 数据表(PDF) 66 Page - Analog Devices |
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AD7779 数据表(HTML) 66 Page - Analog Devices |
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66 / 97 page ![]() AD7779 Data Sheet Rev. 0 | Page 66 of 97 CHANNEL 2 SYNC OFFSET REGISTER Address: 0x00B, Reset: 0x00, Name: CH2_SYNC_OFFSET Channel Sync Offs et 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] CH2_SYNC_OFFSET (R/W) Table 55. Bit Descriptions for CH2_SYNC_OFFSET Bits Bit Name Settings Description Reset Access [7:0] CH2_SYNC_OFFSET Channel Sync Offset 0x0 R/W CHANNEL 3 SYNC OFFSET REGISTER Address: 0x00C, Reset: 0x00, Name: CH3_SYNC_OFFSET Channel Sync Offs et 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] CH3_SYNC_OFFSET (R/W) Table 56. Bit Descriptions for CH3_SYNC_OFFSET Bits Bit Name Settings Description Reset Access [7:0] CH3_SYNC_OFFSET Channel Sync Offset 0x0 R/W CHANNEL 4 SYNC OFFSET REGISTER Address: 0x00D, Reset: 0x00, Name: CH4_SYNC_OFFSET Channel Sync Offs et 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] CH4_SYNC_OFFSET (R/W) Table 57. Bit Descriptions for CH4_SYNC_OFFSET Bits Bit Name Settings Description Reset Access [7:0] CH4_SYNC_OFFSET Channel Sync Offset 0x0 R/W CHANNEL 5 SYNC OFFSET REGISTER Address: 0x00E, Reset: 0x00, Name: CH5_SYNC_OFFSET Channel Sync Offs et 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] CH5_SYNC_OFFSET (R/W) Table 58. Bit Descriptions for CH5_SYNC_OFFSET Bits Bit Name Settings Description Reset Access [7:0] CH5_SYNC_OFFSET Channel Sync Offset 0x0 R/W |
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