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AD7779 数据表(PDF) 2 Page - Analog Devices |
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AD7779 数据表(HTML) 2 Page - Analog Devices |
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2 / 97 page ![]() AD7779 Data Sheet Rev. 0 | Page 2 of 97 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 DOUTx Timing Characterististics............................................. 9 SPI Timing Characterististics ................................................... 10 Synchronization Pins and Reset Timing Characteristics ...... 11 SAR ADC Timing Characterististics ....................................... 12 GPIO SRC Update Timing Characterististics......................... 12 Absolute Maximum Ratings.......................................................... 13 Thermal Resistance .................................................................... 13 ESD Caution................................................................................ 13 Pin Configuration and Function Descriptions........................... 14 Typical Performance Characteristics ........................................... 17 Terminology .................................................................................... 30 RMS Noise and Resolution............................................................ 31 High Resolution Mode............................................................... 31 Low Power Mode........................................................................ 31 Theory of Operation ...................................................................... 32 Analog Inputs.............................................................................. 32 Transfer Function ....................................................................... 33 Core Signal Chain....................................................................... 34 Capacitive PGA........................................................................... 34 Internal Reference and Reference Buffers............................... 34 Integrated LDOs ......................................................................... 35 Clocking and Sampling.............................................................. 35 Digital Reset and Synchronization Pins .................................. 35 Digital Filtering........................................................................... 36 Shutdown Mode.......................................................................... 36 Controlling the AD7779............................................................ 37 Pin Control Mode....................................................................... 37 SPI Control.................................................................................. 39 Digital SPI Interface ................................................................... 42 Diagnostics and Monitoring ......................................................... 45 Self Diagnostics Error ................................................................ 45 Monitoring Using the AD7779 SAR ADC (SPI Control Mode)........................................................................................... 46 Σ-Δ ADC Diagnostics (SPI Control Mode)............................ 48 -Δ Output Data............................................................................. 49 ADC Conversion Output—Header and Data ........................ 49 Sample Rate Converter (SRC) (SPI COntrol MOde) ............ 50 Data Output Interface................................................................ 51 Calculating the CRC Checksum .............................................. 56 Register Summary .......................................................................... 57 Register Details ............................................................................... 61 Channel 0 Configuration Register ........................................... 61 Channel 1 Configuration Register ........................................... 61 Channel 2 Configuration Register ........................................... 62 Channel 3 Configuration Register ........................................... 62 Channel 4 Configuration Register ........................................... 63 Channel 5 Configuration Register ........................................... 63 Channel 6 Configuration Register ........................................... 64 Channel 7 Configuration Register ........................................... 64 Disable Clocks to ADC Channel Register .............................. 65 Channel 0 Sync Offset Register ................................................ 65 Channel 1 Sync Offset Register ................................................ 65 Channel 2 Sync Offset Register ................................................ 66 Channel 3 Sync Offset Register ................................................ 66 Channel 4 Sync Offset Register ................................................ 66 Channel 5 Sync Offset Register ................................................ 66 Channel 6 Sync Offset Register ................................................ 67 Channel 7 Sync Offset Register ................................................ 67 General User Configuration 1 Register................................... 67 General User Configuration 2 Register................................... 68 General User Configuration 3 Register................................... 69 Data Output Format Register ................................................... 69 Main ADC Meter and Reference Mux Control Register ...... 70 Global Diagnostics Mux Register............................................. 71 GPIO Configuration Register................................................... 72 GPIO Data Register.................................................................... 72 Buffer Configuration 1 Register ............................................... 72 Buffer Configuration 2 Register ............................................... 73 Channel 0 Offset Upper Byte Register..................................... 73 Channel 0 Offset Middle Byte Register ................................... 73 Channel 0 Offset Lower Byte Register..................................... 74 Channel 0 Gain Upper Byte Register....................................... 74 Channel 0 Gain Middle Byte Register ..................................... 74 Channel 0 Gain Lower Byte Register....................................... 74 |
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