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CGS701AV 数据表(PDF) 5 Page - National Semiconductor (TI) |
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CGS701AV 数据表(HTML) 5 Page - National Semiconductor (TI) |
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5 / 10 page ![]() CGS701A AC Electrical Characteristics Over recommended operating free air temperature range All typical values are measured at VCC e 5V TA e 25 C Symbol Parameter VCC e 45V–55V Units Notes FIN e 25 to 40 MHz T e 0 Cto a70 C CL e Circuit 1 RL e Circuit 1 Min Typ Max trise Output Rise CLK4 08V to 26V (Note 1 7) CLK2 10V to VCC b 10V 20 ns CLK1 10V to VCC b 10V All 08V to 20V 15 tfall Output Fall CLK4 26V to 08V (Note 1 7) CLK2 VCC b 10V to 10V 20 ns CLK1 VCC b 10V to 10V All 08V to 20V 15 tSKEW Maximum Edge-to- a to a Edges CLK1 CLK1 400 (Note 2 7) Edge Output Skew a to a Edges CLK1 CLK4 1000 ps a to a Edges CLK2 CLK4 1000 tLOCK Time to Lock the Output to the Synch Input 20 100 m s tCYCLE Output Duty Cycle CLK1 Outputs 49 51 (Note 3 7) CLK2 Output 49 51 % CLK4 Output 35 65 JLT Output Jitter (Long Term) 03 ns (Note 4 7) tPD Propogation Delay from XTALIN to FBKOUT b 03 a 03 ns (Notes 2 4 5 6 7) FMIN Minimum XTALIN Frequency 15 MHz FMAX Maximum XTALIN Frequency 43 MHz Note 1 trise and tfall parameters are measured at the pin of the device Note 2 Skew is measured at 50% of VCC for CLK1 and CLK2 while it is being measured at 14V for CLK4 Limits are guaranteed by design Note 3 Output duty cycle is measured at VDD 2 for CLK1 and CLK2 while it is being measured at 14V for CLK4 Limits are guaranteed by design Note 4 Jitter parameter is characterized and is guaranteed by design only It measures the uncertainty of either the positive or the negative edge over 1000 cycles It is also measured at output levels of VCC 2 Refer to Figure 3 for further explanation Note 5 Measured from the ref input to any output pin The length of the feedback and XTALIN traces will impact this delay time Note 6 This parameter includes pin-to-pin skew longterm jitter over 1000 cycles part-to-part variation as well as propagation delay thru the device Note 7 The GNDA pins of the 701 must be as free of noise as possible for minimum jitter Separate analog ground plane is recommended for the PCB Also the VCCA pin requires extra filtering to further reduce noise Ferrite beads for filtering and bypass capacitors are suggested for the VCCA pin Circuit 1 Test Circuit TLF11920 – 4 http www nationalcom 5 |
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