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ADAV4601

Rev. B | Page 17 of 60

FUNCTIONAL DESCRIPTIONS

POWER-UP SEQUENCE

The following sequence provides an overview of how to

initialize the IC:

Apply power to the ADAV4601.

Enable PLL via an I2C write and wait 15 ms for PLL to lock.

Power up via an I2C write to the global power-up bit in the

initialization control register (0x0000).

A default flow is automatically loaded on power-up. If a

user-defined flow is loaded, see the Loading a Custom

Audio Processing Flow section for additional information.

Depending on the I/O blocks required, other steps may

need to be taken; for example, headphone outputs may

need to be tristated. See the ADC Inputs, DAC Voltage

Outputs, PWM Outputs, Headphone Output and S/PDIF

Input/Output sections that describe the I/O blocks in detail.

Unmute.

MASTER CLOCK OSCILLATOR

Internally, the ADAV4601 operates synchronously to the master

MCLKI input. All internal system clocks are generated from this

single clock input using an internal PLL. This MCLKI input

can also be generated by an external crystal oscillator connected

to the MCLKI/XIN pin or by using a simple crystal oscillator

connected across MCLKI/XIN and XOUT. By default, the master

clock frequency is 24.576 MHz; however, by using the internal

dividers, an MCLKI of 12.288 MHz, 6.144 MHz, and 3.072 MHz

are also supported.

OSC

DIVIDER

DIVIDER WORD

[÷8, ÷4, ÷2, ÷1]

3.072MHz

PLL

REFERENCE

CLOCK

MASTER CLOCK FREQUENCY

[24.576MHz, 12.288MHz,

6.144MHz, 3.072MHz]

I2C

EXTERNAL CLOCK/

CRYSTAL

Figure 21. Master Clock

Figure 22 shows the external circuit recommended for proper

operation when using a crystal oscillator. Due to the effect of

stray capacitance, consideration must be given to the value of

C1 and C2 when calculating the desired CLOAD for the crystal.

LOAD

)

)(

(

where:

Cpg1

and Cpg2 are the pin to ground capacitances.

is the PCB stray capacitance.

A good rule of thumb is to approximate Cpg1 and Cpg2 to be

between 5 pF and 10 pF and CS to be between 2 pF and 3 pF.

XIN

XOUT

Figure 22. Circuit for Crystal Resonator

I2C INTERFACE

The ADAV4601 supports a 2-wire serial (I2C compatible)

microprocessor bus driving multiple peripherals. The ADAV4601

is controlled by an external I2C master device, such as a micro-

controller. The ADAV4601 is in slave mode on the I2C bus, except

during self-boot. While the ADAV4601 is self-booting, it becomes

the master, and the EEPROM, which contains the ROMs to be

booted, is the slave. When the self-boot process is complete, the

ADAV4601 reverts to slave mode on the I2C bus. No other devices

should access the I2C bus while the ADAV4601 is self-booting

(refer to the Application Layer section and the Loading a

Custom Audio Processing Flow section).

Initially, all devices on the I2C bus are in an idle state, wherein

the devices monitor the SDA and SCL lines for a start condition

and the proper address. The I2C master initiates a data transfer by

establishing a start condition, defined by a high-to-low transition

on SDA while SCL remains high. This indicates that an address/

data stream follows. All devices on the bus respond to the start

condition and read the next byte (7bit address plus the R/W bit)

MSB first. The device that recognizes the transmitted address

responds by pulling the data line low during the ninth clock

pulse. This ninth bit is known as an acknowledge bit.

All other devices on the bus revert to an idle condition. The R/W

bit determines the direction of the data. A Logic Level 0 on the

LSB of the first byte means the master writes information to the

peripheral. A Logic Level 1 on the LSB of the first byte means the

master reads information from the peripheral. A data transfer takes

place until a stop condition is encountered. A stop condition occurs

when SDA transitions from low to high while SCL is held high.

The ADAV4601 determines its I2C device address by sampling

the SDO0 pin after reset. Internally, the SDO0 pin is sampled by

four MCLKI edges to determine the state of the pin (high or

low). Because the pin has an internal pull-down resistor default,

the address of the ADAV4601 is 0x34 (write) and 0x35 (read).

An alternate address, 0x36 (write) and 0x37 (read), is available

by tying the SDO0 pin to ODVDD via a 10 kΩ resistor. The I2C

interface supports a clock frequency of up to 400 kHz.

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