ADAV4601 datasheet(28/60 Pages) AD

28 / 60 page

ADAV4601

Rev. B | Page 28 of 60

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

TIME (ms)

Constant Time Update

A constant time update is calculated by adding a step value that

is determined after each target is loaded. The equation for this

step size is

Step = (Target Data − Slew Data)/(Number of Steps)

Figure 44 shows a plot of the target/slew RAM operating in

constant time mode. For this example, 128 steps are used to reach

the target value. This type of ramping takes a fixed amount of time

for a given number of steps, regardless of the difference in the

initial state and the target value. Figure 45 shows a plot of a

constant time ramp from −80 dB to −6 dB (half scale) using

128 steps; therefore, the ramp takes the same amount of time

as the previous ramp from −80 dB to 0 dB. A constant time

decreasing ramp plot is shown in Figure 46.

Figure 46. Slew RAM—Constant Time Update Decreasing Ramp, Full Scale

TIME (ms)

1.0

0.8

0.6

0.4

0.2

–0.6

–0.4

–0.2

–0.8

–1.0

LAYOUT RECOMMENDATIONS

Parts Placement

The priority for decoupling is VREF, FILTA, FILTD, PLL_LF, and

finally the supplies. For effective decoupling in all cases, make sure

the decoupling capacitor sees the respective ground pin before the

ground plane.

The 1 nF and 100 nF bypass capacitors for the PLL loop filter

should be placed as close as possible to the ADAV4601. All 10 μF

and 0.1 μF bypass capacitors, which are recommended for every

analog, digital, and power/ground pair, should also be placed as

close as possible to the ADAV4601 with priority given to the 0.1 μF

capacitor.

The ADC input voltage-to-current resistors and the ADC

current set resistor should be placed as close as possible to the

respective pins.

Figure 44. Slew RAM—Constant Time Update Increasing Ramp, Full Scale

TIME (ms)

1.0

0.8

0.6

0.4

0.2

–0.6

–0.4

–0.2

–0.8

–1.0

Crystal Oscillator Circuit

All traces in the crystal oscillator circuit (see Figure 22) should be

kept as short as possible to minimize stray capacitance. In addition,

avoid long board traces connected to any of these components

because such traces may affect crystal startup and operation.

PWM Outputs

All PWM output differential pairs should be matched in length,

that is, PWM1A = PWM1B, PWM2A = PWM2B.

Grounding

A split ground plane should be used in the layout of the ADAV4601

with the analog and digital grounds connected underneath the

ADAV4601 using a single link. This layout is to avoid possible

ground loop currents in the analog and digital ground planes.

Components in the analog signal path should be placed away

from the digital signals. No signal traces should cross the gap

between the planes.

Figure 45. Slew RAM—Constant Time Update Increasing Ramp, Half Scale

ADAV4601 数据表(PDF) 28 Page - Analog Devices

ADAV4601 数据表(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载

链接网址

ADAV4601 数据表(PDF) 28 Page - Analog Devices

ADAV4601 数据表(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表 下载

链接网址

数据表下载