Pin Descriptions

Pin

Name

Description

1

Reset

Manual Reset Input (High True)

2

NRZ-NRZI

NRZ-to-NRZI Conversion Control (NRZ=High, NRZI=Low)

3

Test Out

Test Out (BIST Pass/Fail Indicator)

4V

SS

Negative Power Supply Input (Digital Logic)

5V

SS

Negative Power Supply Input (Digital Logic)

6V

DD

Positive Power Supply Input (Digital Logic)

7V

DD

Positive Power Supply Input (Digital Logic)

8

EDH Force

Force Insertion of New EDH and Flags in Serial Output Data (High True)

9

EDH Enable

EDH Enable Input (Low True)

10

SMPTE Mode

SMPTE/non-SMPTE Mode Select Input (SMPTE Mode=Low)

11

N/C

No Connect

12

D0

Parallel Data Input (Internal Pull-Down to V

13

D1

Parallel Data Input (Internal Pull-Down to V

14

D2

Parallel Data Input (Internal Pull-Down to V

15

D3

Parallel Data Input (Internal Pull-Down to V

16

D4

Parallel Data Input (Internal Pull-Down to V

17

D5

Parallel Data Input (Internal Pull-Down to V

18

D6

Parallel Data Input (Internal Pull-Down to V

19

D7

Parallel Data Input (Internal Pull-Down to V

20

D8

Parallel Data Input (Internal Pull-Down to V

21

D9

Parallel Data Input (Internal Pull-Down to V

22

P

CLK

Parallel Clock Input (Internal Pull-Down to V

23

H/Line-Field b0 (LSB)

H-Bit Output (Component); Line-Field ID (Composite)

24

V/Line-Field b1

V-Bit Output (Component); Line-Field ID (Composite)

25

F/Line-Field b2 (MSB)

F-Bit Output (Component); Line-Field ID (Composite)

26

Lock Detect

Lock Detector Output (High True)

27

V

SSO

Negative Power Supply Input (PLL Supply)

28

V

DDO

Positive Power Supply Input (PLL Supply)

29

TPG Enable

TPG Enable (High True)

30

V

SSOD

Negative Power Supply Input (PLL Digital Supply)

31

V

SSOD

Negative Power Supply Input (PLL Digital Supply)

32

V

DDOD

Positive Power Supply Input (PLL Digital Supply)

33

V

DDOD

Positive Power Supply Input (PLL Digital Supply)

34

N/C

No Connect

35

R

REF

Output Level Reference Resistor (1.69 k

Ω, 1% Nominal Value)

36

V

DDOD

Positive Power Supply Input (PLL Digital Supply)

37

V

SSSD

Negative Power Supply Input (Output Driver)

38

SDO

Serial Data True Output

39

SDO

Serial Data Complement Output

40

V

DDSD

Positive Power Supply Input (Output Driver)

41

Sync Detect Enable

Parallel Data Sync Detection Enable Input (Low True)

42

NSP

New Sync Position Output

43

ANC

Ancilliary Data Header Flag Output

44

NTSC/PAL

NTSC/PAL Mode Indicator Output (PAL=High, NTSC=Low)

Note: All CMOS/TTL inputs have internal pull-down devices.

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