CLC030VEC datasheet(13/29 Pages) NSC

13 / 29 page

Device Operation (Continued)

the CLC030 has detected the video format being received.

This format detect function involves determination of the

major raster parameters such as line length, number of video

lines in a frame, and so forth. This is done so that information

like line numbering can be correctly inserted. The PLL itself

will have locked in 200 microseconds (HD rates) or less.

However, resolution of all raster parameters may take the

majority of a frame.

SERIAL DATA OUTPUT DRIVER

The serial data outputs provide low-skew complimentary or

differential signals. The output buffer is a current-mode de-

sign and is intended to drive AC-coupled and terminated,

Ω coaxial cables. The driver automatically adjusts rise and

fall times depending upon the data rate being processed.

Output levels are 800 mV

P-P ±10% into 75Ω AC-coupled

loads. The 75

Ω resistors connected to the SDO outputs

function both as drain-load and back-matching resistors.

Series back-matching resistors are not used with this output

type.

The serial output level is controlled by the value of R

REFLVL

and R

REFPRE connected to pin 53 and pin 52, respectively.

The R

REFLVL resistor sets the peak-to-peak level of the

output signal to the required SMPTE nominal level. The

REFPRE resistor sets the value of a pre-emphasis current

which is active during the rise and fall times of the HD-rate

output signal. The value of R

REFLVL is normally 4.75 KΩ,

±1%. The value of R

REFPRE is normally 4.75 KΩ, ±1%. The

voltage present at these pins is approximately +1.3Vdc. The

rise and fall times of this output buffer design automatically

adjust and are different for the HD and SD data rate condi-

tions. The output buffer is quiescent when the device is in an

out-of-lock condition. The output will become active after the

PLL is locked and a valid format has been detected. Sepa-

rate power feeds are provided for the serial output driver:

SSSD, pins 54, 55, and 59; VDDSD, pin 51; and VDDLS, pin

57.

CAUTION: This output buffer is not designed or specified for

driving 50

Ω or other impedance loads.

POWER SUPPLIES, POWER-ON-RESET AND RESET

INPUT

The CLC030 requires two power supplies, 2.5V for the core

logic functions and 3.3V for the I/O functions. The supplies

must be applied to the device in proper sequence. The 3.3V

supply must be applied prior to or coincident with the 2.5V

supply. Application of the 2.5V supply must not precede the

3.3V supply. It is recommended that the 3.3V supply be

configured or designed so as to control application of the

2.5V supply in order to satisfy this sequencing requirement.

The CLC030 has an automatic, power-on-reset circuit. Re-

set initializes the device and clears TRS detection circuitry,

all latches, registers, counters and polynomial generators,

sets the EDH/CRC characters to 00h and disables the serial

output.

Table 1 lists the initial conditions of the configuration

and control registers. An active-HIGH-true, manual reset

input is available at pin 64. The reset input has an internal

pull-down device and may be considered inactive when

unconnected.

Important: When power is first applied to the device or

following a reset, the Ancilliary and Control Data Port

must be initialized to receive data. This is done by toggling

ACLK three times.

TEST PATTERN GENERATOR (TPG) AND BUILT-IN

SELF-TEST (BIST)

The CLC030 includes a built-in test pattern generator

(TPG). Four test pattern types are available for all data rates,

all HD and SD formats, NTSC and PAL standards, and 4x3

and 16x9 raster sizes. The test patterns are: flat-field black,

PLL pathological, equalizer (EQ) pathological and a 75%,

8-colour vertical bar pattern. The pathologicals follow the

recommendations of SMPTE RP 178-1996 regarding the

test data used. The colour bar pattern has optional band-

width limiting coding in the chroma and luma data transitions

between bars. The VPG FILTER ENABLE bit in the VIDEO

INFO 0 control register enables the colour bar filter function.

The default condition of VPG FILTER ENABLE is OFF.

The TPG also functions as a built-in self-test (BIST) which

can verify device functionality. The BIST function performs a

comprehensive go/no-go test of the device. The test may be

run using any of the HD colour bar test patterns or one of two

SD test patterns, either a 270 Mb/s NTSC full-field colour bar

or a PAL PLL pathological, as the test data pattern. Data is

supplied internally in the input data register, processed

through the device and tested for errors using either the EDH

system for SD or the CRC system for HD. A go/no-go indi-

cation is logged in the Pass/Fail bit of the TEST 0 control

multifunction I/O port.

TPG and BIST operation is initiated by loading the code for

the desired test pattern into the Test Pattern Select [5:0]

bits of the TEST 0 register.

Table 5 gives the available test

patterns and codes. (Recall also the requirement to initialize

the ancilliary data port control logic by clocking ACLK at

least three (3) complete cycles before attempting to load the

first register address). In the default power-on state, TPG

Enable appears as bit 7 on the multi-function I/O port. The

TPG is run by applying the appropriate frequency at the

VCLK input for the format and rate selected and then setting

the TPG Enable input on the multi-function I/O port, or by

setting the TPG Enable bit in the TEST 0 register.

Important: If the TPG Enable input of the I/O port is in its

default mapping and is not being used to enable the TPG

mode, attempting to enable TPG operation by setting bit 6 of

the TEST 0 register will not cause the TPG to operate. This

is because the low logic level at the I/O port input pulldown

overrides the high level being written to the register. The

result is the TPG does not run.

The Pass/Fail bit in the TEST 0 control register indicates the

test status. If no errors have been detected, this bit will be

set to logic-1 approximately 2 field intervals after TPG En-

able is set. If errors have been detected in the internal

circuitry of the CLC030, Pass/Fail will remain reset to a

logic-0. The TPG or BIST is halted by resetting TPG Enable.

The serial output data is present at the SDO outputs during

TPG or BIST operation.

Caution ! When attempting to use the TPG or BIST imme-

diately after applying power or resetting the device, the TPG

defaults to the 270Mbps SD rate and expects a VCLK clock

frequency of 27MHz as input. This is because the code for

the test pattern in the TEST 0 register is set to 00h (525 line,

30 frame, 27MHz, NTSC 4x3 reference black). Attempting to

apply a VCLK frequency higher than the device expects,

according to the setting in the TEST 0 register, may result in

the PLL locking up while attempting to slew to its maximum

possible frequency. This situation is not recoverable by the

use of the device RESET input. To recover from this condi-

tion, power must be removed and re-applied to the device.

Proper conditioning of the VCLK input, which does not have

CLC030VEC 数据表(PDF) 13 Page - National Semiconductor (TI)

CLC030VEC 数据表(HTML) 13 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

数据表下载