TDA8030 datasheet(18/57 Pages) PHILIPS

18 / 57 page

2003 Jul 04

Philips Semiconductors

Product speciﬁcation

USB smart card reader (OTP or ROM)

TDA8030; TDA8031

8.1.4

ISO UART REGISTERS

8.1.4.1

UART transmit register

When the microcontroller wants to transmit a character to

the card, it writes the data in direct convention in this

The transmission:

• Starts at the end of this writing (2 clock cycles after the

rising edge of WR) if the previous character has been

transmitted and if the extra guard time has expired

• Starts at the end of the extra guard time if this one has

not expired

• Starts at 13.5 ETU in manual mode and 15 ETU in

automatic mode if the previous character has been

NAKed by the card; see Section 8.1.4.4

• Does not start if the transmission of the previous

character is not completed.

When the transmission is completed:

• In T = 0, bit TBE is set at 11.5 ETU, and bit PE in the

event of parity error

• In T = 1, bit TBE is set at 10.5 ETU.

In the event of synchronous cards (bit SAN set within

UCR2), UT0 is only relevant and is copied on the I/O of the

card. It is possible to write within the UTR before setting

the transmission mode, which may be useful in some

cases.

Table 9

UART transmit register (address 0DH; write only); note 1

Note

1. All bits are cleared after reset.

76543210

UT7

UT6

UT5

UT4

UT3

UT2

UT1

UT0

8.1.4.2

UART receive register

When the microcontroller wants to read data from the card,

it reads it from this register in direct convention.

In the event of synchronous cards, only UR0 is relevant

and is a copy of the state of the card I/O.

In the event of parity error:

• The bit PE in the status register USR is set at 10.5 ETU

and INT0 falls LOW

• In protocol T = 0, the received byte is not stored in URR;

In protocol T = 1, the received byte is stored.

In both protocols, when a character has been stored, then

the bit RBF in the status register USR is set at 10.5 ETU.

This bit is reset when the character has been read from the

URR.

When the URR is empty, then bit FE (in the MSR) is set as

long as no character has been received.

Table 10 UART receive register (address 0DH; read only); note 1

Note

1. All bits are cleared after reset.

76543210

UR7

UR6

UR5

UR4

UR3

UR2

UR1

UR0

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