Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

SUPPLY

Supply Voltage

4.5

5

5.5

V

Supply Current

9

mA

POR Pull Down Resistor

pin 20

40

K

Ω

POR Threshold

2.5

V

FILTER(measured an pin 4 FILOUT)

Center Frequency

56.5

57

57.5

KHz

BW

3dB Bandwidth

2.5

3

3.5

KHz

G

Gain

f = 57KHz

18

20

22

dB

A

Attenuation

∆f = +4KHz

18

50

35

22

80

50

dB

dB

dB

∆Ph

Phase non linearity

A (see note1)

B (see note1)

C (see note1)

0.5

1

2

5

7.5

10

DEG

DEG

DEG

Input Impedance

100

160

200

K

Ω

S/N

Signal to Noise Ratio

30

40

dB

Maximum Input Signal Capability

f = 19KHz; T3 < –40dB (see note2)

f = 57KHz (RDS + ARI)

1

50

Vrms

mVrms

Load Impedance

Pin 4

100

K

Ω

CROSS DETECTOR

RA

Resistance pin 3-4

15

21

28

K

Ω

OSCILLATOR

Oscillator Frequency

4.332

8.664

MHz

MHz

VCLL

Clock Input level LOW (pin 10)

1

V

VCLH

Clock Input Level HIGH (pin 10)

4

V

Output Amplitude (pin 9)

4.5

(*) FSEL pin has an internal 40K

Ω pull down resistor A 4.332MHz QUARTZ must be used (**) A 8.664MHz QUARTZ must be used.

DEMODULATOR

Max Oscillator Deviation

+ 1.2

KHz

RDS Detection Sensitivity

1

mVrms

ARI Detection Sensitivity

3

mVrms

RDS Lockup Time

100

ms

Output HIGH Voltage

4

V

Output LOW Voltage

1

V

Data Rate for RDS

RDCL pin

1187.5

Hz

RDDA Transition versus RDCL

(see figure 2)

4.3

µsec

Note(1):

The phase non linearity is defined as:

∆Ph = | -2 φf2 + φf1 + φf3 |

where

φfx is the input-output phase difference at the frequency fx (x = 1,2,3)

TDA7330B

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