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DSP56362AD 数据表(PDF) 14 Page - Motorola, Inc |
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DSP56362AD 数据表(HTML) 14 Page - Motorola, Inc |
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14 / 168 page ![]() 1-6 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions External Memory Expansion Port (Port A) External Address Bus External Data Bus External Bus Control Table 1-5 External Address Bus Signals Signal Name Type State during Reset Signal Description A0–A17 Output Tri-stated Address Bus—When the DSP is the bus master, A0–A17 are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A0–A17 do not change state when external memory spaces are not being accessed. Table 1-6 External Data Bus Signals Signal Name Type State during Reset Signal Description D0–D23 Input/Output Tri-stated Data Bus—When the DSP is the bus master, D0–D23 are active-high, bidirectional input/ outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0–D23 are tri-stated. Table 1-7 External Bus Control Signals Signal Name Type State during Reset Signal Description AA0–AA3/ RAS0– RAS3 Output Tri-stated Address Attribute or Row Address Strobe—When defined as AA, these signals can be used as chip selects or additional address lines. When defined as RAS, these signals can be used as RAS for DRAM interface. These signals are can be tri-stated outputs with programmable polarity. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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