DSP56362AD datasheet(26/168 Pages) MOTOROLA

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DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

Serial Host Interface

SERIAL HOST INTERFACE

The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.

Table 1-10 Serial Host Interface Signals

Signal Name

Signal Type

State

during

Reset

Signal Description

SCK

SCL

Input or

output

Input or

output

Tri-stated

SPI Serial Clock—The SCK signal is an output

when the SPI is configured as a master and a

Schmitt-trigger input when the SPI is configured as

a slave. When the SPI is configured as a master,

the SCK signal is derived from the internal SHI

clock generator. When the SPI is configured as a

slave, the SCK signal is an input, and the clock

signal from the external master synchronizes the

data transfer. The SCK signal is ignored by the SPI

if it is defined as a slave and the slave select (SS)

signal is not asserted. In both the master and slave

SPI devices, data is shifted on one edge of the SCK

signal and is sampled on the opposite edge where

data is stable. Edge polarity is determined by the

SPI transfer protocol.

I2C Serial Clock—SCL carries the clock for I2C bus

transactions in the I2C mode. SCL is a Schmitt-

trigger input when configured as a slave and an

open-drain output when configured as a master.

SCL should be connected to VCC through a pull-up

resistor.

This signal is tri-stated during hardware, software,

and individual reset. Thus, there is no need for an

external pull-up in this state.

This input is 5 V tolerant.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56362AD 数据表(PDF) 26 Page - Motorola, Inc

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